GS81302T38GE-300IT datasheet, PDF

Datasheet> All Categories > storage> storage> GS81302T38GE-300IT

GS81302T38GE-300IT: DescriptionDDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; Categorystorage storage; File Size455KB，32 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

Download Datasheet Parametric View All

GS81302T38GE-300IT Overview

DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS81302T38GE-300IT Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	75497472 bit
Memory IC Type	DDR SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

Preview

Download Datasheet

View All

Preliminary

GS81302T06/11/20/38E-450/400/375/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.5 Clock Latency

• Simultaneous Read and Write SigmaDDR

Interface

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• On-Die Termination (ODT) on Data (D), Byte Write (BW),

and Clock (K, K) inputs

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• Data Valid Pin (QVLD) Support

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

144Mb SigmaDDR

-II+

Burst of 2 SRAM

450 MHz–300 MHz

1.8 V V

1.8 V or 1.5 V I/O

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

SigmaDDR-II™ Family Overview

The GS81302T06/11/20/38E are built in compliance with the

SigmaDDR-II+ SRAM pinout standard for Common I/O

synchronous SRAMs. They are 150,994,944-bit (144Mb)

SRAMs. The GS81302T06/11/20/38E SigmaDDR-II+

SRAMs are just one element in a family of low power, low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

Clocking and Addressing Schemes

The GS81302T06/11/20/38E SigmaDDR-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Because Common I/O SigmaDDR-II+ RAMs always transfer

data in two packets, A0 is internally set to 0 for the first read

or write transfer, and automatically incremented by 1 for the

next transfer. Because the LSB is tied off internally, the

address field of a SigmaDDR-II+ B2 RAM is always one

address pin less than the advertised index depth (e.g., the 8M x

18 has a 4M addressable index).

Parameter Synopsis

-450

tKHKH

tKHQV

2.2 ns

0.37 ns

-400

2.5 ns

0.45 ns

-375

2.66 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

Rev: 1.01a 6/2010

1/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Resources

External grid power supply and self-generated power supply conversion circuit

A practical delay switch circuit

Server preamplifier circuit diagram of parallel op amp

Power carrier amplifier circuit

Computer motherboard circuit diagram 830_15

Battery cold end thermocouple protection circuit

Does the backlight 14-leds in LCD refer to the number of LEDs in the backlight?: For example, the AT070TN92 LCD data sheet says: "backlight 14-leds". Does the "LCD" here refer to the number of LEDs? How are these LCDs connected? Some are marked: 3 in series 6 or other indicators. ...; bigbat MCU

Using nRF24L01 with MicroPython: I saw the nRF24L01 driver in the micropython source code a long time ago, but I never tested it. Yesterday I soldered two modules, modified the GPIO definition, tested the basic communication function...; dcexpert MicroPython Open Source section

How to find MSP430 program examples on TI's official website: Take MSP430Fr6972 as an example:1) Enter the TI official website: http://www.ti.com.cn/2) Enter: msp430fr6972 in the search bar and click go on3) Click the first search result (usually the first one i...; 火辣西米秀 Microcontroller MCU

Industrial grade 485 serial port server: Industrial grade 485 serial port server ZLAN5143BI ZLAN5143BI is a serial port server with RS485/422 serial port isolation, which can effectively isolate the influence of interference on RS485 bus on ...; wzzlin123 51mcu

C2000 Software Serial Interface (SCI) Implementation Method: The C2000 Piccolo series MCU chips generally integrate 1-2 hardware SCI (UART). Sometimes, due to cost or layout area considerations, only small packages or models with less resources can be selected,...; 灞波儿奔 Microcontroller MCU

Introduction to the ideas and methods of MCU serial port to CAN: In the process of embedded product development, you may face the problem of insufficient CAN channels. How to choose a suitable conversion module to solve this problem? The following will explain the ...; Jacktang Microcontroller MCU

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components