WMS512K8V-XXX
512Kx8 MONOLITHIC SRAM
EVOLUTIONARY PINOUT
32 DIP
32 CSOJ (DE)
PRELIMINARY*
FEATURES
s
Access Times 70, 85, 100, 120ns
s
MIL-STD-883 Compliant Devices Available
s
Low Voltage Operation
s
Evolutionary, Corner Power/Ground Pinout
JEDEC Approved
• 32 pin Ceramic DIP (Package 300)
• 32 lead Ceramic SOJ (Package 101)
s
Commercial, Industrial and Military Temperature Ranges
s
Low Power CMOS
s
Low Voltage Operation
• 3.3V
±
10% Power Supply
s
Low Power Data Retention
s
TTL Compatible Inputs and Outputs
*
This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
2
SRAM MONOLITHICS
TOP VIEW
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTION
A
0-18
I/O
0-7
CS
OE
WE
V
CC
GND
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
+3.3V Power Supply
Ground
April 1998
1
White Microelectronics • Phoenix, AZ • (602) 437-1520
WMS512K8V-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
Vcc+0.5
150
7.0
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
X
H
X
H
L
H
TRUTH TABLE
WE
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
2
SRAM MONOLITHICS
Junction Temperature
Supply Voltage
RECOMMENDED OPERATING CONDITIONS
Parameter
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Symbol
V
CC
V
IH
V
IL
TA
Min
3.0
2.2
-0.3
-55
Max
3.6
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
Input capacitance
Output capacitance
CAPACITANCE
(T
A
= +25°C)
Symbol
C
IN
C
OUT
Condition
V
IN
= 0V, f = 1.0MHz
V
OUT
= 0V, f = 1.0MHz
Max Unit
12
12
pF
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(V
CC
= 3.3V, GND = 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Conditions
Min
V
CC
= 3.6, V
IN
= GND to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz, Vcc = 3.6
CS = V
IH
, OE = V
IH
, f = 5MHz, Vcc = 3.6
I
OL
= 2.1mA, V
CC
= 3.0
I
OH
= -1.0mA, V
CC
= 3.0
2.4
Max
10
10
25
400
0.4
µA
µA
mA
µA
V
V
Units
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
White Microelectronics • Phoenix, AZ • (602) 437-1520
2
WMS512K8V-XXX
AC CHARACTERISTICS
(V
CC
= 3.3V, GND = 0V, T
A
= -55°C to +125°C)
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
t
OLZ
1
Symbol
Min
70
-70
Max
Min
85
70
5
70
35
10
5
25
25
10
5
5
-85
Max
-100
Min
100
85
5
85
40
10
5
25
25
35
35
100
50
10
5
100
5
Max
Min
120
-120
Max
Units
ns
120
ns
ns
120
60
ns
ns
ns
ns
35
35
ns
ns
2
SRAM MONOLITHICS
1
t
CHZ
1
t
OHZ
1
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(V
CC
= 3.3V, GND = 0V, T
A
= -55°C to +125°C)
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold from Write Time
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
Symbol
Min
70
60
60
30
50
0
5
5
-70
Max
Min
85
75
75
35
50
0
5
5
25
0
0
-85
Max
Min
100
80
80
40
60
0
5
5
25
0
-100
Max
Min
120
100
100
40
60
0
5
5
35
0
-120
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
35
ns
ns
t
WHZ
t
DH
1
1. This parameter is guaranteed by design but not tested.
AC TEST CIRCUIT
I
OL
Current Source
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
D.U.T.
C
eff
= 50 pf
V
Z
≈
1.5V
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
3
White Microelectronics • Phoenix, AZ • (602) 437-1520
WMS512K8V-XXX
TIMING WAVEFORM - READ CYCLE
t
RC
ADDRESS
t
AA
2
SRAM MONOLITHICS
CS
t
RC
ADDRESS
t
ACS
t
CLZ
OE
t
CHZ
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
t
OHZ
DATA VALID
READ CYCLE 1 (CS = OE = V
IL
, WE = V
IH
)
READ CYCLE 2 (WE = V
IH
)
WRITE CYCLE - WE CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
CS
t
AH
t
AS
WE
t
WP
t
OW
t
WHZ
t
DW
t
DH
DATA I/O
DATA VALID
WRITE CYCLE 1, WE CONTROLLED
WRITE CYCLE - CS CONTROLLED
t
WC
ADDRESS
WS32K32-XHX
t
AS
t
AW
t
CW
t
AH
CS
t
WP
WE
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, CS CONTROLLED
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
WMS512K8V-XXX
PACKAGE 101:
32 LEAD, CERAMIC SOJ
21.1 (0.830)
±
0.25 (0.010)
0.2 (0.008)
±
0.05 (0.002)
3.96 (0.156) MAX
0.89 (0.035)
Radius TYP
2
9.55 (0.376)
±
0.25 (0.010)
11.3 (0.446)
±
0.2 (0.009)
SRAM MONOLITHICS
1.27 (0.050)
±
0.25 (0.010)
PIN 1 IDENTIFIER
1.27 (0.050) TYP
19.1 (0.750) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 300:
32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED
42.4 (1.670)
±
0.4 (0.016)
15.04 (0.592)
±
0.3 (0.012)
4.34 (0.171)
±
0.79 (0.031)
PIN 1 IDENTIFIER
3.2 (0.125) MIN
0.84 (0.033)
±
0.4 (0.014)
2.5 (0.100)
TYP
1.27 (0.050)
±
0.1 (0.005)
0.46 (0.018)
±
0.05 (0.002)
0.25 (0.010)
±
0.05 (0.002)
15.25 (0.600)
±
0.25 (0.010)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
5
White Microelectronics • Phoenix, AZ • (602) 437-1520
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