S71WS512NC0BAIAZ2 datasheet, PDF

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S71WS512NC0BAIAZ2: DescriptionMemory Circuit, 16MX16, CMOS, PBGA84, 11.60 X 8 MM, 1.20 MM HEIGHT, LEAD FREE COMPLIANT, FBGA-84; Categorystorage storage; File Size4MB，153 Pages; ManufacturerSPANSION; Websitehttp://www.spansion.com/; Environmental Compliance

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S71WS512NC0BAIAZ2 Overview

Memory Circuit, 16MX16, CMOS, PBGA84, 11.60 X 8 MM, 1.20 MM HEIGHT, LEAD FREE COMPLIANT, FBGA-84

S71WS512NC0BAIAZ2 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SPANSION
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	84
Reach Compliance Code	compliant
Other features	PSRAM IS ORGANIZED AS 4M X 16; SYNCHRONOUS BURST MODE ALSO POSSIBLE
JESD-30 code	R-PBGA-B84
JESD-609 code	e1
length	11.6 mm
memory density	268435456 bit
Memory IC Type	MEMORY CIRCUIT
memory width	16
Humidity sensitivity level	3
Number of functions	1
Number of terminals	84
word count	16777216 words
character code	16000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	16MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	8 mm

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S71WS512Nx0/S71WS256Nx0 Based MCPs

Stacked Multi-chip Product (MCP)

256/512 Megabit (32M/16M x 16 bit) CMOS

1.8 Volt-only Simultaneous Read/Write,

Burst-mode Flash Memory with

128/64Megabit (8M/4M x 16-Bit) CosmoRAM

ADVANCE

INFORMATION

Distinctive Characteristics

MCP Features

Power supply voltage of 1.7 to 1.95V

Burst Speed: 54MHz

Packages: 8 x 11.6 mm, 9 x 12 mm

Operating Temperature

-25°C to +85°C

-40°C to +85°C

General Description

The S71WS Series is a product line of stacked Multi-chip Product (MCP) packages

and consists of

One or more flash memory die

CosmoRAM-compatible pSRAM

The products covered by this document are listed in the table below. For details

about their specifications, please refer to the individual constituent datasheet for

further details.

Flash Density

512Mb

pSRAM Density

128Mb

64Mb

32Mb

16Mb

S71WS512ND0

S71WS512NC0

256Mb

S71WS256ND0

S71WS256NC0

128Mb

64Mb

Publication Number

S71WS512/256Nx0_CS

Revision

Amendment

Issue Date

November 8, 2004

A d v a n c e

I n f o r m a t i o n

S71WS512Nx0/S71WS256Nx0 Based MCPs

Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1

MCP Features ................................................................................................... 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . 1

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .4

MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .5

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .6

CosmoRAM Based Pinout ..................................................................................6

MCP Look-ahead Connection Diagram .........................................................7

Input/Output Descriptions . . . . . . . . . . . . . . . . . . . .8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .9

Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . 10

256Mb WS256N Flash + 64Mb pSRAM ........................................................ 10

256Mb - WS256N Flash + 128 pSRAM ......................................................... 10

2x 256Mb—WS512N Flash + 64Mb pSRAM .................................................11

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 12

FEA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP

Compatible Package ........................................................................................... 12

TSD084—84-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 9.0 mm MCP

Compatible Package ............................................................................................13

TLA084—84-ball Fine-Pitch Ball Grid Array (FBGA) 11.6x8.0x1.2 mm

MCP Compatible Package ................................................................................14

S29WSxxxN MirrorBit™ Flash Family

General Description . . . . . . . . . . . . . . . . . . . . . . . 15

Application Notes ........................................................................................... 18

Specification Bulletins .................................................................................... 18

Drivers and Software Support .................................................................... 18

CAD Modeling Support ................................................................................ 18

Technical Support ........................................................................................... 18

Spansion LLC Locations ........................................................ 18

Table 4.2. S29WS128N Sector & Memory Address Map .......... 20

Table 4.3. S29WS064N Sector & Memory Address Map .......... 21

Table 5.4. Device Operations .............................................. 22

Table 5.7. Address Latency for 5 Wait States (≤ 68 MHz) ........ 24

Table 5.8. Address Latency for 4 Wait States (≤ 54 MHz) ........ 25

Table 5.9. Address Latency for 3 Wait States (≤ 40 MHz) ........ 25

Table 5.10. Address/Boundary Crossing Latency for 6 Wait States

(≤ 80 MHz) ....................................................................... 25

Table 5.11. Address/Boundary Crossing Latency for 5 Wait States

(≤ 68 MHz) ....................................................................... 25

Table 5.12. Address/Boundary Crossing Latency for 4 Wait States

(≤ 54 MHz) ....................................................................... 25

Table 5.13. Address/Boundary Crossing Latency for 3 Wait States

(≤ 40 MHz) ....................................................................... 25

Figure 5.2. Synchronous Read ............................................. 26

Table 5.14. Burst Address Groups ....................................... 27

Table 5.15. Configuration Register ....................................... 28

Table 5.16. Autoselect Addresses ........................................ 29

Table 5.17. Autoselect Entry ............................................... 29

Table 5.18. Autoselect Exit ................................................. 30

Figure 5.19. Single Word Program ........................................ 32

Table 5.20. Single Word Program ........................................ 33

Table 5.21. Write Buffer Program ........................................ 35

Figure 5.22. Write Buffer Programming Operation .................. 36

Table 5.23. Sector Erase .................................................... 38

Figure 5.24. Sector Erase Operation ..................................... 39

Table 5.25. Chip Erase ....................................................... 40

Table 5.26. Erase Suspend ................................................. 41

Table 5.27. Erase Resume .................................................. 41

Table 5.28. Program Suspend ............................................. 42

Table 5.29. Program Resume .............................................. 42

Table 5.30. Unlock Bypass Entry .......................................... 43

Table 5.31. Unlock Bypass Program ..................................... 44

Table 5.32. Unlock Bypass Reset ......................................... 44

Figure 5.33. Write Operation Status Flowchart....................... 46

Table 5.34. DQ6 and DQ2 Indications ................................... 48

Table 5.35. Write Operation Status ...................................... 49

Table 5.36. Reset .............................................................. 51

Figure 6.2. Lock Register Program Algorithm......................... 57

Table 8.2. SecSi Sector Entry .............................................. 62

Table 8.3. SecSi Sector Program .......................................... 63

Table 8.4. SecSi Sector Entry .............................................. 63

Figure 9.2. Maximum Positive Overshoot Waveform ............... 64

Figure 9.3. Test Setup........................................................ 65

Figure 9.4. Input Waveforms and Measurement Levels ........... 66

Figure 9.5. V

Power-up Diagram....................................... 66

Figure 9.6. CLK Characterization.......................................... 68

Figure 9.7. CLK Synchronous Burst Mode Read...................... 70

Figure 9.8. 8-word Linear Burst with Wrap Around................. 71

Figure 9.9. 8-word Linear Burst without Wrap Around ............ 71

Figure 9.10. Linear Burst with RDY Set One Cycle Before Data 72

Figure 9.11. Asynchronous Mode Read ................................. 73

Figure 9.12. Reset Timings ................................................. 74

Figure 9.2. Chip/Sector Erase Operation Timings: WE# Latched

Addresses......................................................................... 76

Figure 9.13. Asynchronous Program Operation Timings: WE#

Latched Addresses............................................................. 77

Figure 9.14. Synchronous Program Operation Timings:

CLK Latched Addresses ...................................................... 78

Figure 9.15. Accelerated Unlock Bypass Programming Timing.. 79

Figure 9.16. Data# Polling Timings

(During Embedded Algorithm)............................................. 79

Figure 9.17. Toggle Bit Timings (During Embedded Algorithm) 80

Figure 9.18. Synchronous Data Polling

Timings/Toggle Bit Timings ................................................. 80

Figure 9.19. DQ2 vs. DQ6................................................... 81

Figure 9.20. Latency with Boundary Crossing when

Frequency > 66 MHz.......................................................... 81

Figure 9.21. Latency with Boundary Crossing into Program/

Erase Bank ....................................................................... 82

Figure 9.22. Example of Wait States Insertion ....................... 83

Figure 9.23. Back-to-Back Read/Write Cycle Timings.............. 84

Table 10.2. Sector Protection Commands .............................. 89

Table 10.3. CFI Query Identification String ............................ 90

Table 10.4. System Interface String ..................................... 91

Table 10.5. Device Geometry Definition ................................ 91

Table 10.6. Primary Vendor-Specific Extended Query ............. 92

CosmoRAM

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Pin Description (32M) . . . . . . . . . . . . . . . . . . . . . . . 98

Functional Description . . . . . . . . . . . . . . . . . . . . . 99

Asynchronous Operation (Page Mode) .......................................................99

Functional Description . . . . . . . . . . . . . . . . . . . . 100

Synchronous Operation (Burst Mode) ...................................................... 100

State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Initial/Standby State ............................................................................................101

Figure 11.7. Initial Standby State Diagram ......................... 101

Asynchronous Operation State .....................................................................101

Figure 11.8. Asynchronous Operation State Diagram............ 101

Synchronous Operation State .......................................................................102

Figure 11.9. Synchronous Operation Diagram...................... 102

Functional Description . . . . . . . . . . . . . . . . . . . . 102

Power-up ..............................................................................................................102

S71WS512Nx0/S71WS256Nx0

S71WS512/256Nx0_CSA0 November 8, 2004

A d v a n c e

I n f o r m a t i o n

Configuration Register ....................................................................................102

CR Set Sequence ...............................................................................................102

Address Key ....................................................................................................... 104

Power Down ...................................................................................................... 105

Burst Read/Write Operation ........................................................................ 105

Figure 11.10. Burst Read Operation.................................... 106

Figure 11.11. Burst Write Operation ................................... 106

CLK Input Function ..........................................................................................106

ADV# Input Function ...................................................................................... 107

WAIT# Output Function ................................................................................ 107

Latency ................................................................................................................. 108

Figure 11.12. Read Latency Diagram .................................. 108

Address Latch by ADV# .................................................................................109

Burst Length .......................................................................................................109

Single Write ........................................................................................................109

Write Control .....................................................................................................110

Figure 11.13. Write Controls.............................................. 110

Burst Read Suspend ...........................................................................................110

Figure 11.14. Burst Read Suspend Diagram......................... 111

Burst Write Suspend .......................................................................................... 111

Figure 11.15. Burst Write Suspend Diagram ........................ 111

Burst Read Termination .................................................................................... 111

Figure 11.16. Burst Read Termination Diagram .................... 112

Burst Write Termination ................................................................................ 112

Figure 11.17. Burst Write Termination Diagram.................... 112

Absolute Maximum Ratings . . . . . . . . . . . . . . . . .

Recommended Operating Conditions (See

Warning Below) . . . . . . . . . . . . . . . . . . . . . . . . . .

Package Pin Capacitance . . . . . . . . . . . . . . . . . . .

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .

113

114

115

Read Operation .................................................................................................. 115

Write Operation ................................................................................................ 117

Synchronous Operation - Clock Input (Burst Mode) .............................118

Synchronous Operation - Address Latch (Burst Mode) ........................118

Synchronous Read Operation (Burst Mode) ............................................. 119

Synchronous Write Operation (Burst Mode) ..........................................120

Power Down Parameters ................................................................................ 121

Other Timing Parameters ............................................................................... 121

AC Test Conditions .......................................................................................... 121

AC Measurement Output Load Circuit ..................................................... 122

Figure 11.18. Output Load Circuit....................................... 122

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 123

Figure 11.19. Asynchronous Read Timing #1-1 (Basic Timing) 123

Figure 11.20. Asynchronous Read Timing #1-2 (Basic Timing) 123

Figure 11.21. Asynchronous Read Timing #2 (OE# & Address

Access)........................................................................... 124

Figure 11.22. Asynchronous Read Timing #3 (LB# / UB# Byte

Access)........................................................................... 124

Figure 11.23. Asynchronous Read Timing #4 (Page Address Access

after CE1# Control Access)................................................ 125

Figure 11.24. Asynchronous Read Timing #5 (Random and Page

Address Access)............................................................... 125

Figure 11.25. Asynchronous Write

Timing #1-1 (Basic Timing) ............................................... 126

Figure 11.26. Asynchronous Write

Timing #1-2 (Basic Timing) ............................................... 126

Figure 11.27. Asynchronous Write Timing #2 (WE# Control). 127

Figure 11.28. Asynchronous Write Timing #3-1 (WE# / LB# / UB#

Byte Write Control).......................................................... 127

Figure 11.29. Asynchronous Write Timing #3-2 (WE# / LB# / UB#

Byte Write Control).......................................................... 128

Figure 11.30. Asynchronous Write Timing #3-3 (WE# / LB# / UB#

Byte Write Control).......................................................... 128

Figure 11.31. Asynchronous Write Timing #3-4 (WE# / LB# / UB#

Byte Write Control).......................................................... 129

Figure 11.32. Asynchronous Read / Write Timing #1-1 (CE1#

Control) ......................................................................... 129

Figure 11.33. Asynchronous Read / Write Timing #1-2 (CE1# /

WE# / OE# Control) ........................................................ 130

Figure 11.34. Asynchronous Read / Write Timing #2 (OE#, WE#

Control) ......................................................................... 130

Figure 11.35. Asynchronous Read / Write Timing #3 (OE,# WE#,

LB#, UB# Control)........................................................... 131

Figure 11.36. Clock Input Timing....................................... 131

Figure 11.37. Address Latch Timing (Synchronous Mode)...... 132

Figure 11.38. 32M Synchronous Read

Timing #1 (OE# Control).................................................. 133

Figure 11.39. 32M Synchronous Read

Timing #2 (CE1# Control) ................................................ 134

Figure 11.40. 32M Synchronous Read

Timing #3 (ADV# Control)................................................ 135

Figure 11.41. Synchronous Read - WAIT# Output Timing

(Continuous Read)........................................................... 136

Figure 11.42. 64M Synchronous Read

Timing #1 (OE# Control).................................................. 137

Figure 11.43. 64M Synchronous Read

Timing #2 (CE1# Control) ................................................ 138

Figure 11.44. 64M Synchronous Read

Timing #3 (ADV# Control)................................................ 139

Figure 11.45. Synchronous Write

Timing #1 (WE# Level Control) ......................................... 140

Figure 11.46. Synchronous Write Timing #2 (WE# Single Clock

Pulse Control) ................................................................. 141

Figure 11.47. Synchronous Write Timing #3 (ADV# Control). 142

Figure 11.48. Synchronous Write Timing #4 (WE# Level Control,

Single Write)................................................................... 143

Figure 11.49. 32M Synchronous Read to Write Timing #1(CE1#

Control) ......................................................................... 144

Figure 11.50. 32M Synchronous Read to Write Timing #2(ADV#

Control) ......................................................................... 145

Figure 11.51. 64M Synchronous Read to Write Timing #1(CE1#

Control) ......................................................................... 146

Figure 11.52. 64M Synchronous Read to Write Timing #2(ADV#

Control) ......................................................................... 147

Figure 11.53. Synchronous Write to Read Timing #1 (CE1#

Control) ......................................................................... 148

Figure 11.54. Synchronous Write to Read Timing #2 (ADV#

Control) ......................................................................... 149

Figure 11.55. Power-up Timing #1..................................... 150

Figure 11.56. Power-up Timing #2.................................... 150

Figure 11.57. Power Down Entry and Exit Timing................. 150

Figure 11.58. Standby Entry Timing after Read or Write ....... 151

Figure 11.59. Configuration Register Set Timing #1 (Asynchronous

Operation)...................................................................... 151

Figure 11.60. Configuration Register Set Timing #2 (Synchronous

Operation)...................................................................... 152

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 153

November 8, 2004 S71WS512/256Nx0_CSA0

S71WS512Nx0/S71WS256Nx0

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