Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care
should be taken that the voltage applied on these pins does not exceed the V
CC
applied to the device. This will ensure proper operation.
Ordering Information
NM
93
C
XX
LZ
E
XXX
Package
N
M8
MT8
None
V
E
Blank
L
LZ
56
C
CS
Interface
93
Letter Description
8-pin DIP
8-pin SO
8-pin TSSOP
0 to 70°C
-40 to +125°C
-40 to +85°C
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
2048 bits
CMOS
Data protect and sequential
read
MICROWIRE
Temp. Range
Voltage Operating Range
Density
Fairchild Memory Prefix
2
NM93C56 Rev. E
www.fairchildsemi.com
NM93C56 2048-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
ESD rating
-65°C to +150°C
+6.5V to -0.3V
Operating Conditions
Ambient Operating Temperature
NM93C56
NM93C56E
NM93C56V
Power Supply (V
CC
)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
4.5V to 5.5V
+300°C
2000V
DC and AC Electrical Characteristics
V
CC
= 4.5V to 5.5V unless otherwise specified
Symbol
I
CCA
I
CCS
I
IL
I
OL
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
f
SK
t
SKH
t
SKL
t
SKS
t
CS
t
CSS
t
DH
t
DIS
t
CSH
t
DIH
t
PD
t
SV
t
DF
t
WP
Parameter
Operating Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
Minimum CS Low Time
CS Setup Time
DO Hold Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
Conditions
CS = V
IH
, SK=1.0 MHz
CS = V
IL
V
IN
= 0V to V
CC
(Note 2)
Min
Max
1
50
±-1
Units
mA
µA
µA
V
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
-0.1
2
I
OL
= 2.1 mA
I
OH
= -400
µA
I
OL
= 10
µA
I
OH
= -10
µA
(Note 3)
0°C to +70°C
-40°C to +125°C
250
300
250
50
(Note 4)
250
100
70
100
0
20
2.4
0.8
V
CC
+1
0.4
0.2
V
CC
- 0.2
1
500
500
CS = V
IL
100
10
ns
ns
ns
ms
3
NM93C56 Rev. E
www.fairchildsemi.com
NM93C56 2048-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
ESD rating
-65°C to +150°C
+6.5V to -0.3V
Operating Conditions
Ambient Operating Temperature
NM93C56L/LZ
NM93C56LE/LZE
NM93C56LV/LZV
Power Supply (V
CC
)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
2.7V to 5.5V
+300°C
2000V
DC and AC Electrical Characteristics
V
CC
= 2.7V to 5.5V unless otherwise specified
Symbol
I
CCA
I
CCS
Parameter
Operating Current
Standby Current
L
LZ (2.7V to 4.5V)
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
Minimum CS Low Time
CS Setup Time
DO Hold Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
Conditions
CS = V
IH
, SK=1.0 MHz
CS = V
IL
Min
Max
1
10
1
Units
mA
µA
µA
µA
V
V
KHz
µs
µs
µs
µs
µs
ns
µs
ns
µs
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
SK
t
SKH
t
SKL
t
SKS
t
CS
t
CSS
t
DH
t
DIS
t
CSH
t
DIH
t
PD
t
SV
t
DF
t
WP
V
IN
= 0V to V
CC
(Note 2)
-0.1
0.8V
CC
I
OL
= 10µA
I
OH
= -10µA
(Note 3)
0.9V
CC
0
1
1
0.2
(Note 4)
1
0.2
70
0.4
0
0.4
±1
0.15V
CC
V
CC
+1
0.1V
CC
250
2
1
CS = V
IL
0.4
15
µs
µs
µs
ms
Capacitance
T
A
= 25°C, f = 1 MHz (Note 5)
Symbol
C
OUT
C
IN
Note 1:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:
Typical leakage values are in the 20nA range.
Test
Output Capacitance
Input Capacitance
Typ
Max
5
5
Units
pF
pF
Note 3:
The shortest allowable SK clock period = 1/f
SK
(as shown under the f
SK
parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both t
SKH
and t
SKL
limits must be observed. Therefore, it is not
allowable to set 1/f
SK
= t
SKHminimum
+ t
SKLminimum
for shorter SK cycle time operation.
Note 4:
CS (Chip Select) must be brought low (to V
IL
) for an interval of t
CS
in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
AC Test Conditions
V
CC
Range
(Extended Voltage Levels)
Note 5:
This parameter is periodically sampled and not 100% tested.
V
IL
/V
IH
Input Levels
0.3V/1.8V
0.4V/2.4V
V
IL
/V
IH
Timing Level
1.0V
1.0V/2.0V
V
OL
/V
OH
Timing Level
0.8V/1.5V
0.4V/2.4V
I
OL
/I
OH
±10µA
2.1mA/-0.4mA
2.7V
≤
V
CC
≤
5.5V
(TTL Levels)
4.5V
≤
V
CC
≤
5.5V
Output Load: 1 TTL Gate (C
L
= 100 pF)
4
NM93C56 Rev. E
www.fairchildsemi.com
NM93C56 2048-Bit Serial CMOS EEPROM
(MICROWIRE
TM
Synchronous Bus)
Pin Description
Chip Select (CS)
This is an active high input pin to NM93C56 EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low.
Microwire Interface
A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array, a set of 7 instructions are implemented on NM93C56.
The format of each instruction is listed under Table 1.
Instruction
Each of the 7 instructions is explained under individual instruction
descriptions.
Start bit
This is a 1-bit field and is the first bit that is clocked into the device
when a Microwire cycle starts. This bit has to be “1” for a valid cycle
to begin. Any number of preceding “0” can be clocked into the
device before clocking a “1”.
Serial Clock (SK)
This is an input pin to the device and is generated by the master that
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input informa-
tion (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge
of this clock input. This pin is gated by CS signal.
Opcode
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with 2 MSB of address field) select a
particular instruction to be executed.
Serial Input (DI)
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input informa-
tion (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
Address Field
This is an 8-bit field and should immediately follow the Opcode bits.
In NM93C56, only the LSB 7 bits are used for address decoding
during READ, WRITE and ERASE instructions. During these three
instructions (READ, WRITE and ERASE), the MSB is “don’t care”
(can be 0 or 1). During all other instructions, the MSB 2 bits are used
to decode instruction (along with Opcode bits).
Serial Output (DO)
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Data Field
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
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