Datasheet
JUNE 1999
LXT6051
STM-1/0 SDH Overhead Terminator
General Description
The LXT6051 Overhead Terminator implements the
Regenerator Section Termination, Multiplexer Section
Termination and Higher Order Path Termination in STM-0
(51Mb/s) and STM-1 (155Mb/s) multiplexers. It provides
micro-controller access for performance monitoring, alarm
detection and configuration for transmit and receive paths.
When used with the LXT6251 (21E1 Mapper), a complete
solution for a 21 E1 or a 63 E1 Multiplexer is created.
The LXT6051 is compliant with the latest releases of ITU-
T G.703 and G.707. It provides all the alarm and control
features to easily implement the multiplexer described in
ITU-T G.783.
Revision 2.0
Features
• Performs Regenerator Section, Multiplexer Section,
and Higher Order Path Overhead Processing for
STM-1 and STM-0 signals.
• Byte parallel interface for STM-1 or STM-0, with
byte alignment performed internally. Serial NRZ or
B3ZS interface option for STM-0.
• Demultiplexes STM-0/STM-1 signals to Telecom Bus
output with optional pointer processor re-timing.
• Multiplexes Telecom Bus data into STM-0 or STM-1
signals with pointer processing.
• Compatible with 1+1 protected ITU architecture.
• Records all RSOH, MSOH, and HPOH alarms. One
second counters for B1, B2, B3, M1 REI and G1 REI.
• Full J0/J1 trace identifier processing.
• Serial access to STM-1 user-defined, media-
dependent and national bytes.
• Dedicated pins for serial access or pass-through
feature for E1, E2, F1, F2, F3, D1-D3 & D4-D12
bytes.
• Low power CMOS technology with 3.3V core and 5V
I/O in PQFP-208 package.
• IEEE 1149.1 Boundary Scan (JTAG) support.
Applications
• SDH Terminal Mux/ADM for microwave radio
• ADM fiber ring Mux
• Digital Loop Carrier (NGDLC) Systems
• Digital Cross-Connect System
LXT6051 Block Diagram
S E TS
LXT6051
OHT
TX
TB us Tim ing
6.48M /19.44M C lock
Telecom B us Data
4
POH
S erial A ccesses
MMSP
B us
SOH
S erial A ccesses
Transm it
M aster
Clock In
Tx Clock out
Data
1 or 8 (STM -0 )
8 (STM -1)
Transm it
Telecom
Bu s Add
In terface
AU -3/4 &
V C-3/4
Transm it P rocessor
(HP T, M S A (P P ))
S TM -0 / S TM -1
Transm it S ection
Term ination &
P ro tection Fu nction
(RS T, M S T, M S P )
LXT6251
21 C hannel
M apper
Telecom B us Data
6.48M /19.44M C lock
TB us Tim ing
Receive
Telecom
Bu s
Drop
In terface
M icrocontroller Interface (Intel/Motorola selectable)
AU -3/4 &
V C-3/4
Receive P rocesso r
(M S A, H P T &
Retim ing)
O ptional retim ing
Clock & tim ing
POH
S erial A ccesses
Data
Clock
LO S
1 or 8 (STM -0 )
8 (STM -1)
STM -0/1
Line
Interface
S TM -0 / S TM -1
Receive S ectio n
Term ination &
P rotection Function
(RS T, M S T, M S P )
RX
4
DM S P
B us
SOH
S erial A ccesses
LX T
60 51 _
DS
_
RE V
2.
FM
- 7/6 /99
Refer to www.level1.com for most current information.
LXT6051 STM-1/0 SDH Overhead Terminator
TABLE OF CONTENTS
Table Of Contents ....................................................................................................................................... .... 2
Pin Assignments And Signal Description ................................................................................................ .... 7
Functional Description ............................................................................................................................... ..19
Transmit Data Flow .................................................................................................................................. ..19
Receive Data Flow ................................................. ...................................................................... ............ ..20
Reference Clocks .................................................................................................................................... ..22
Modes of Operation .................................................................................................................................. ..22
Chip Configuration .................................................................................................................................... . 22
Repeater Mode Configuration .................................................................................................................. ..22
Terminal Mode Configuration (No Protection) .......................................................................................... ..23
Receive Side Telecom Bus Timing Source ......................................................................................... ..23
Transmit Side Telecom Bus Timing Source ........................................................................................ ..23
Add and Drop Configuration ..................................................................................................................... ..25
Receive Side Telecom Bus Timing Source ......................................................................................... ..25
Transmit Side Telecom Bus Timing Source ........................................................................................ ..25
Updating the Transmit AU Pointer Justification Event Counters ......................................................... ..26
Terminal Protection Mode ........................................................................................................................ ..26
Receive Side Telecom Bus Timing Source ......................................................................................... ..26
Transmit Side Telecom Bus Timing Source ........................................................................................ ..26
Receiver Default Operation ...................................................................................................................... ..26
Serial Interface .................................................................................................................................... ..26
Parallel Interface ................................................................................................................................. ..26
Clock Distribution and Reference ........................................................................................................ . 28
Framer ................................................................................................................................................ ..28
Regenerator Section Receiver ........................................................................................................ ..30
Multiplexer Section Receiver .............................................................................................................. ..31
Multiplexer Section Protection (MSP) Block ....................................................................................... ..32
Pointer Recovery ................................................................................................................................ ..32
Higher Order Path Receiver ............................................................................................................... ..32
Re-Timing Function ............................................................................................................................. . 33
Transmitter Default Operation .................................................................................................................. ..34
Higher Order Path Transmitter ................................................................................................................. ..34
Transmit Pointer Processing Function ..................................................................................................... ..36
Transmit Multiplex Section Protection (MSP Block) .................................................................................. ..36
Multiplexer Section Transmitter ................................................................................................................ . 36
Regenerator Section Transmitter ............................................................................................................. ..38
Parallel Interface ...................................................................................................................................... ..39
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LXT6051 Table Of Contents
Serial Interface .................................................................................................................................... . 39
Clock Distribution and Reference ........................................................................................................ . 40
Functional Timing ........................................................................................................................................ . 42
Transmit Frame Parallel Timing ............................................................................................................... . 42
Transmit Frame Serial Timing .................................................................................................................. . 43
Receive Re-timing Functional Timing ..................................................................................................... . 44
Telecom Bus Interface .............................................................................................................................. . 45
Multiplexer Telecom Bus Terminal Mode .................................................................................................. . 45
Multiplexer Telecom Bus ADM Mode ....................................................................................................... . 46
Demultiplexer Telecom Bus (Terminal or ADM) Mode ............................................................................... . 46
Protection Bus Interface Timing .............................................................................................................. . 50
Transmitter “Master” in 1+1 Protection Configuration ............................................................................... . 50
Transmitter “Slave” in 1+1 Protection Configuration ................................................................................. . 50
Receive”Master” in 1+1 Protection Configuration ..................................................................................... . 51
Receive “Slave” Configuration (1+1 Protection) ....................................................................................... . 51
OverHead Byte Access Timing ................................................................................................................ . 54
F2 and F3 Digital Channel Functional Timing .......................................................................................... . 54
Transmit side access ........................................................................................................................... . 54
Receive side access ........................................................................................................................... . 54
E1, E2 and F1 Orderwire Channel Functional Timing ............................................................................... . 55
Transmit Timing ................................................................................................................................... . 55
Receive timing...................................................................................................................................... 55
HPOH Bytes Serial Access Functional Timing ......................................................................................... . 56
Transmit serial HPOH Timing .............................................................................................................. . 56
Receive Serial HPOH Timing .............................................................................................................. . 57
SOH Overhead Access Functional Timing ............................................................................................... . 58
Transmit Side SOH Serial Timing ........................................................................................................ . 58
Receive Side SOH Serial Timing ........................................................................................................ . 59
D1 to D3 Data Communication Channel Functional Timing ...................................................................... . 60
Transmit Side Access........................................................................................................................... 60
Receive Side Access .......................................................................................................................... . 60
D4 to D12 Data Communication Channel ................................................................................................. 61
Transmit Side Access .......................................................................................................................... . 61
Receive Side Access ........................................................................................................................... 61
BIP Receive Functional Timing ............................................................................................................... . 62
Test Specifications ...................................................................................................................................... . 63
Microprocessor Interface & Register Description .................................................................................... . 81
Microcontroller Interface .......................................................................................................................... . 81
Intel interface ............................................................................................................................................ . 81
Motorola interface ..................................................................................................................................... . 81
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LXT6051 STM-1/0 SDH Overhead Terminator
Interrupt Handling .................................................................................................................................... ..81
Interrupt Sources ................................................................................................................................ ..81
Interrupt Enables ................................................................................................................................ ..82
Interrupt Clearing ................................................................................................................................ ..82
Status Registers Access ..................................................................................................................... ..82
C2, K3, K2, K1 and S1 Receive Byte Registers Access...................................................................... ..82
Counter Reading ...................................................................................................................................... ..82
Register Address Map ............................................................................................................................. ..83
Global Registers ....................................................................................................................................... ..88
OCR1—Operational Configuration 1 (50H) ............................................................................................. ..88
OCR2—Operational Configuration 2 (51H) ............................................................................................. ..89
CHIP_ID—Chip ID Number (52H) ........................................................................................................... ..90
BUF_ACNTS—Buffer All Counters (54H) ................................................................................................ ..90
Receive Regenerator Section Termination Registers ............................................................................ ..91
R_RSTC1—Receive RST Configuration 1 (40H) .................................................................................... ..91
R_RSTC2—Receive RST Configuration 2 (47H) .................................................................................... ..92
LOF_LMN—Loss of Frame L, M, & N Configuration (41–42H) ................................................................ ..92
OOF_ECNT—Out Of Frame Event Counter (44–43H) ............................................................................. ..93
B1_ERRCNT—B1 Error Counter (46–45H) ............................................................................................. ..93
Receive Regenerator and Multiplexer Section Termination Registers ................................................. ..94
J0_RSTR_C—J0 Expected String Control (0EH) .................................................................................... ..94
J0_RSTR_D—J0 Expected String Data (0FH) ........................................................................................ ..94
WINSZ_SB2—Window Size for Setting ExcB2ErrSt (1C–1BH)................................................................ . 95
CWIN_SB2—Consecutive Windows for Setting ExcB2ErrSt (1DH) ......................................................... ..95
E#_EXCWIN—Number of Errs/Win for Excessively Errored Window (1EH) ............................................ ..95
WINSZ_C2—Window Size for Clearing ExcB2ErrSt (16–15H) ................................................................ ..95
CWIN_CB2—Consecutive Windows for Clearing ExcB2ErrSt (17H)........................................................ . 96
E#_NEXCWIN—Number of Errs/Win for Non-Excessively Errored Window (18H) .................................. ..96
B2_BLKCNT—B2 Block Error Counter (11–10H) .................................................................................... ..96
B2_BIPCNT—B2 BIP Error Counter (14–12H) ........................................................................................ ..96
MR_BLKCNT—MST REI Block Error Counter (0A–09H) ......................................................................... ..97
MR_BIPCNT—MST REI BIP Error Counter (0D–0BH) ............................................................................ ..97
R_K1—Received K1 byte (00H) .............................................................................................................. ..97
R_K2—Received K2 Byte (01H) .............................................................................................................. ..97
R_S1—Received S1 byte (02H) .............................................................................................................. ..97
R_NU1_8—Received Nu1_8 byte (03H) ................................................................................................. ..98
R_NU1_9—Received Nu1_9 byte (04H) ................................................................................................. ..98
R_NU2_8—Received Nu2_8 byte (05H) ................................................................................................. ..98
R_NU2__9—Received Nu2_9 byte (06H) ............................................................................................... ..98
R_NU9_8—Received Nu9_8 byte (07H) ................................................................................................. ..98
R_NU9_9—Received Nu9_9 byte (08H) ................................................................................................. ..98
Receive Multiplexer Section Protection Registers ................................................................................. ..99
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LXT6051 Table Of Contents
R_MSP_C—Receive MSP Configuration (20H) ....................................................................................... . 99
R_MSP_OP—Receive MSP Operational (21H) ....................................................................................... . 99
R_PROTK1—Received K1 byte on Protection Bus from Slave (22H) ...................................................... 100
R_PROTK2—Received K2 byte on Protection Bus from Slave (23H) ...................................................... 100
Receive Multiplexer Section Adaptation Registers ................................................................................ 100
R_MSA_C—Receive MSA Configuration (90H) ....................................................................................... 100
R_AU_NCNT—Receive Negative AU Pointer Justification Event Counter (92–91H) ............................... 101
R_AU_PCNT—Receive Positive AU Pointer Justification Event Counter (94–93H) ................................. 101
Receive HighOrder Path Termination Registers .................................................................................... 102
R_HPT_C1—Receive HPT Configuration 1 Register (80H) ...................................................................... 102
R_HPT_C2—Receive HPT Configuration 2 Register (81H) ...................................................................... 103
J1_RSTR_C—J1 Expected String Control Register (8AH) ....................................................................... 104
J1_RSTR_D—J1 Expected String Data Register (8BH) ........................................................................... 104
EXP_C2—Expected C2 byte Register (82H) ........................................................................................... 104
R_C2—Received C2 byte Register (83H) ................................................................................................ 104
R_K3—Received K3 byte Register (84H) ................................................................................................ 104
R_HPT_RDI—Received HPT RDI Bits Register (85H) ............................................................................. 105
B3_ECNT—B3 Error Event Counter (87–86H) ........................................................................................ 105
HPTREI_CNT—HPT REI Counter (89–88H) ........................................................................................... 105
Transmit Regenerator and Multiplexer Section Termination Registers ................................................ 105
T_RMST_OP1—Transmit RMST Operational 1 Register (30H) ............................................................... 105
T_RMST_OP2—Transmit RMST Operational 2 Register (1AH) ............................................................... 107
T_SC1_SOH—Transmit Source Configuration 1 for SOH bytes Register (60H) ...................................... 108
T_SC2_SOH—Transmit Source Configuration 2 for SOH bytes Register (61H) ...................................... 109
T_SC3_SOH—Transmit Source Configuration 3 for SOH Bytes Register (62H) ...................................... 110
T_SC4_SOH—Transmit Source Configuration 4 for SOH Bytes Register (63H) ...................................... 111
J0_TSTR_C—J0 Transmit String Control Register (3AH) ......................................................................... 112
JO_TSTR_D—J0 Transmit String Data Register (3BH) ............................................................................ 113
MP_TNU1_8—Microprocessor Provided Transmit Nu1_8 Byte (31H) ...................................................... 113
MP_TNU1_9—Microprocessor Provided Transmit Nu1_9 Byte Register (32H) ....................................... 113
MP_TNU2_8—Microprocessor Provided Transmit Nu2_8 Byte (33H) ...................................................... 113
MP_TNU2_9—Microprocessor Provided Transmit Nu2_9 Byte Register (34H) ....................................... 113
MP_TNU9_8—Microprocessor Provided Transmit Nu9_8 Byte (35H) ...................................................... 114
MP_TNU9_9—Microprocessor Provided Transmit Nu9_9 Byte (36H) ...................................................... 114
MP_TK1—Microprocessor Provided Transmit K1 Byte Register (37H) .................................................... 114
MP_TK2—Microprocessor Provided Transmit K2 Byte Register (38H) .................................................... 114
MP_TS1—Microprocessor Provided Transmit S1 Byte Register (39H) .................................................... 114
Transmit Multiplexer Section Adaptation Registers 115
T_AU_NCNT—Transmit Negative AU Pointer Justification Event Counter (E3–E2H).............................. 115
T_AU_PCNT—Transmit Positive AU Pointer Justification Event Counter (E5–E4H) ............................... 115
Transmit HighOrder Path Termination Registers .................................................................................... 116
T_SC_HPOH—Transmit Source Configuration for HPOH bytes (70H) .................................................... 116
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