GS832218AD-375MT datasheet, PDF

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GS832218AD-375MT: DescriptionCache SRAM, 2MX18, 4.2ns, CMOS, PBGA165, FPBGA-165; Categorystorage storage; File Size488KB，35 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS832218AD-375MT Overview

Cache SRAM, 2MX18, 4.2ns, CMOS, PBGA165, FPBGA-165

GS832218AD-375MT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	GSI Technology
Objectid	1155411603
package instruction	LBGA, BGA165,11X15,40
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
compound_id	13328644
Maximum access time	4.2 ns
Other features	IT ALSO OPERATES AT 3 V TO 3.6 V SUPPLY VOLTAGE
Maximum clock frequency (fCLK)	375 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
length	15 mm
memory density	37748736 bit
Memory IC Type	CACHE SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	2MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
power supply	2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.09 A
Minimum standby current	2.3 V
Maximum slew rate	0.36 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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GS832218/36A(B/D)-375M

119 & 165 BGA

Military Temp

Features

• Military Temperature Range

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V +10%/–10% core power supply

• 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-bump and 165-bump BGA packages

2M x 18, 1M x 36

36Mb S/DCD Sync Burst SRAMs

375 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

SCD and DCD Pipelined Reads

The GS832218/36A(B/D)-375M is a SCD (Single Cycle Deselect)

and DCD (Dual Cycle Deselect) pipelined synchronous SRAM.

DCD SRAMs pipeline disable commands to the same degree as

read commands. SCD SRAMs pipeline deselect commands one

stage less than read commands. SCD RAMs begin turning off

their outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the SCD

mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write control

inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low)

for multi-drop bus applications and normal drive strength (ZQ

floating or high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Core and Interface Voltages

The GS83218/36A(B/D)-375M operates on a 2.5 V or 3.3 V

power supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

DDQ

) pins are used to decouple output noise from

the internal circuits and are 3.3 V and 2.5 V compatible.

Functional Description

Applications

The GS832218/36A(B/D)-375M is a

37,748,736

-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications, ranging

from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no degradation of chip performance.

Parameter Synopsis

tCycle

Curr

(x18)

Curr

(x36)

tCycle

Curr

(x18)

Curr

(x36)

-375M

2.5

2.66

400

475

4.2

295

360

Unit

Pipeline

3-1-1-1

Flow Through

2-1-1-1

Rev: 1.01 3/2014

1/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832218AD-375MT Related Products

	GS832218AD-375MT	GS832236AB-375M	GS832236AB-375MT	GS832218AB-375MT
Description	Cache SRAM, 2MX18, 4.2ns, CMOS, PBGA165, FPBGA-165	Cache SRAM, 1MX36, 4.2ns, CMOS, PBGA119, FPBGA-119	Cache SRAM, 1MX36, 4.2ns, CMOS, PBGA119, FPBGA-119	Cache SRAM, 2MX18, 4.2ns, CMOS, PBGA119, FPBGA-119
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
package instruction	LBGA, BGA165,11X15,40	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B
Maximum access time	4.2 ns	4.2 ns	4.2 ns	4.2 ns
Other features	IT ALSO OPERATES AT 3 V TO 3.6 V SUPPLY VOLTAGE	IT ALSO OPERATES AT 3 V TO 3.6 V SUPPLY VOLTAGE	IT ALSO OPERATES AT 3 V TO 3.6 V SUPPLY VOLTAGE	IT ALSO OPERATES AT 3 V TO 3.6 V SUPPLY VOLTAGE
Maximum clock frequency (fCLK)	375 MHz	375 MHz	375 MHz	375 MHz
I/O type	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B165	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119
length	15 mm	22 mm	22 mm	22 mm
memory density	37748736 bit	37748736 bit	37748736 bit	37748736 bit
Memory IC Type	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
memory width	18	36	36	18
Number of functions	1	1	1	1
Number of terminals	165	119	119	119
word count	2097152 words	1048576 words	1048576 words	2097152 words
character code	2000000	1000000	1000000	2000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C
organize	2MX18	1MX36	1MX36	2MX18
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA165,11X15,40	BGA119,7X17,50	BGA119,7X17,50	BGA119,7X17,50
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
power supply	2.5/3.3 V	2.5/3.3 V	2.5/3.3 V	2.5/3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.4 mm	1.99 mm	1.99 mm	1.99 mm
Maximum standby current	0.09 A	0.09 A	0.09 A	0.09 A
Minimum standby current	2.3 V	2.3 V	2.3 V	2.3 V
Maximum slew rate	0.36 mA	0.4 mA	0.4 mA	0.36 mA
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	13 mm	14 mm	14 mm	14 mm

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