IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B
IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B
512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' STATE BUS
SYNCHRONOUS SRAM
FEBRUARY 2014
ADVANCED INFORMATION
FEATURES
•
100 percent bus utilization
•
No wait cycles between Read and Write
•
Internal self-timed write cycle
•
Individual Byte Write Control
•
Single R/W (Read/Write) control pin
•
Clock controlled, registered address, data and
control
•
Interleaved or linear burst sequence control
using MODE input
•
Three chip enables for simple depth
expansion and address pipelining
•
Power Down mode
•
Common data inputs and data outputs
•
/CKE pin to enable clock and suspend
operation
•
JEDEC 100-pin QFP, 165-ball BGA and 119-
ball BGA packages
•
Power supply:
NLP: V
DD
3.3V (± 5%), V
DDQ
3.3V/2.5V (± 5%)
NVP: V
DD
2.5V (± 5%), V
DDQ
2.5V (± 5%)
NVVP: V
DD
1.8V (± 5%), V
DDQ
1.8V (± 5%)
•
JTAG Boundary Scan for BGA packages
•
Commercial, Industrial and Automotive (x36)
temperature support
•
Lead-free available
•
For leaded option, please contact ISSI.
DESCRIPTION
The 18Meg product family features high-speed,
low-power synchronous static RAMs designed to
provide a burstable, high-performance, 'no wait'
state, device for networking and communications
applications. They are organized as 512K words
by 36 bits and 1024K words by 18 bits, fabricated
with
ISSI's
advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles
are eliminated when the bus switches from read
to write, or write to read. This device integrates a
2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single
monolithic circuit.
All synchronous inputs pass through registers are
controlled by a positive-edge-triggered single
clock input. Operations may be suspended and all
synchronous inputs ignored when Clock Enable,
/CKE is HIGH. In this state the internal device will
hold their previous values.
All Read, Write and Deselect cycles are initiated
by the ADV input. When the ADV is HIGH the
internal burst counter is incremented. New
external addresses can be loaded when ADV is
LOW.
Write cycles are internally self-timed and are
initiated by the rising edge of the clock inputs and
when /WE is LOW. Separate byte enables allow
individual bytes to be written.
A burst mode pin (MODE) defines the order of the
burst sequence. When tied HIGH, the interleaved
burst sequence is selected. When tied LOW, the
linear burst sequence is selected.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle time
Frequency
-250
2.6
4
250
-200
3.0
5
200
Units
ns
ns
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at
any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein.
Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders
for products.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
2/13/2014
1
IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B
IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B
PIN CONFIGURATION
512K x 36, 165-Ball BGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWc
/BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/BWb
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
/CKE
/WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
ADV
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
/CKE
A0,A1
A
ADV
MODE
/CE,CE2,/CE2
/WE
/BWx (x=a-d)
/OE
DQx
DQPx
TCK,TDI,
TDO,TMS
ZZ
NC
V
DD
V
DDQ
V
SS
Pin Name
Synchronous Clock
Clock Enable
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address
Advance/Load
Burst Sequence Selection
Synchronous Chip Enable
Synchronous Read/Write Control
Input
Synchronous Byte Write Inputs
Output Enable
Data Inputs/Outputs
Parity Data I/O
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
Bottom View
165-Ball, 13 mm x 15mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
2/13/2014
3
IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B
IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B
512K x 32, 165-Ball BGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWc
/BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
/BWb
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
/CKE
/WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
ADV
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
NC
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
NC
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
/CKE
A0,A1
A
ADV
MODE
/CE,CE2,/CE2
/WE
/BWx (x=a-d)
/OE
DQx
TCK,TDI,
TDO,TMS
ZZ
NC
V
DD
V
DDQ
V
SS
Pin Name
Synchronous Clock
Clock Enable
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address
Advance/Load
Burst Sequence Selection
Synchronous Chip Enable
Synchronous Read/Write Control
Input
Synchronous Byte Write Inputs
Output Enable
Data Inputs/Outputs
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
Bottom View
165-Ball, 13 mm x 15mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
2/13/2014
4
IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B
IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B
1024K x 18, 165-Ball BGA (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
MODE
A
A
NC
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
NC
NC
NC
/CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/BWb
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
/BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
/CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1*
A0*
/CKE
/WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
ADV
/OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
CLK
/CKE
A0,A1
A
ADV
MODE
/CE,CE2,/CE2
/WE
/BWx (x=a-b)
/OE
DQx
DQPx
TCK,TDI,
TDO,TMS
ZZ
NC
V
DD
V
DDQ
V
SS
Pin Name
Synchronous Clock
Clock Enable
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address
Advance/Load
Burst Sequence Selection
Synchronous Chip Enable
Synchronous Read/Write Control
Input
Synchronous Byte Write Inputs
Output Enable
Data Inputs/Outputs
Parity Data I/O
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
Bottom View
165-Ball, 13 mm x 15mm BGA
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 00A
2/13/2014
5
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