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X28HC256JZ-90

Description
256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM; PDIP28, PLCC32, SOIC28; Temp Range: See Datasheet
Categorystorage    storage   
File Size867KB,19 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
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X28HC256JZ-90 Overview

256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM; PDIP28, PLCC32, SOIC28; Temp Range: See Datasheet

X28HC256JZ-90 Parametric

Parameter NameAttribute value
Brand NameIntersil
MakerRenesas Electronics Corporation
Parts packaging codePDIP, PLCC, SOIC
package instructionQCCJ, LDCC32,.5X.6
Contacts28, 32, 28
Reach Compliance Codecompliant
ECCN codeEAR99
Factory Lead Time21 weeks
Maximum access time90 ns
command user interfaceNO
Data pollingYES
Durability1000000 Write/Erase Cycles
JESD-30 codeR-PQCC-J32
JESD-609 codee3
length13.97 mm
memory density262144 bit
Memory IC TypeEEPROM
memory width8
Humidity sensitivity level3
Number of functions1
Number of terminals32
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC32,.5X.6
Package shapeRECTANGULAR
Package formCHIP CARRIER
page size128 words
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply5 V
Programming voltage5 V
Certification statusNot Qualified
Maximum seat height3.55 mm
Maximum standby current0.0005 A
Maximum slew rate0.06 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
switch bitYES
width11.43 mm
Maximum write cycle time (tWC)5 ms
DATASHEET
X28HC256
256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM
The
X28HC256
is a second generation high performance
CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s
proprietary, textured poly floating gate technology, providing a
highly reliable 5V only nonvolatile memory.
The X28HC256 supports a 128-byte page write operation,
effectively providing a 24µs/byte write cycle, and enabling the
entire memory to be typically rewritten in less than 0.8s. The
X28HC256 also features DATA polling and Toggle bit polling,
two methods of providing early end of write detection. The
X28HC256 also supports the JEDEC standard software data
protection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a minimum
100,000 write cycles per byte and an inherent data retention
of 100 years.
FN8108
Rev 5.00
August 27, 2015
Features
• Access time: 90ns
• Simple byte and page write
- Single 5V supply
- No external high voltages or V
P-P
control circuits
- Self timed
- No erase before write
- No complex programming algorithms
- No overerase problem
• Low power CMOS
- Active: 60mA
- Standby: 500µA
• Software data protection
- Protects data against system level inadvertent writes
• High speed page write capability
• Highly reliable Direct Write
cell
- Endurance: 100,000 cycles
- Data retention: 100 years
• Early end of write detection
- DATA polling
- Toggle bit polling
• RoHS compliant
X BUFFERS
LATCHES AND
DECODER
A
0
TO A
14
ADDRESS
INPUTS
Y BUFFERS
LATCHES AND
DECODER
256k BIT
EEPROM
ARRAY
I/O BUFFERS
AND LATCHES
I/O
0
TO I/O
7
CE
OE
WE
V
CC
V
SS
CONTROL
LOGIC AND
TIMING
DATA INPUTS/OUTPUTS
FIGURE 1. BLOCK DIAGRAM
FN8108 Rev 5.00
August 27, 2015
Page 1 of 19

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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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