Intel: Or increase package interconnect density by more than 10 times through hybrid bonding

At the recent IEEE International Electron Devices Meeting (IEDM), Intel outlined its future development direction, which is to increase the interconnect density of packages by more than 10 times through hybrid bonding, increase transistor scaling area by 30% to 50%, and adopt new quantum computing technology.

According to eeNews, Intel's component research group is working in three key areas: scaling technology to provide more transistors; new silicon capabilities for power and memory gains; and exploring new concepts in physics to revolutionize the way the world computes.

Many of Intel's current semiconductor products began with component research, including strained silicon, high-K metal gate, FinFET transistors, RibbonFET, and packaging technologies including EMIB and Foveros Direct.

The company’s researchers have outlined solutions to the design, process and assembly challenges of hybrid bonding interconnects, discovering a way to increase interconnect density in packages by 10 times.

As early as July 2021, Intel announced plans to launch Foveros Direct to achieve sub-10 micron bump pitch, thereby increasing the interconnect density of 3D stacking by an order of magnitude. In order to enable the ecosystem to benefit from advanced packaging, Intel also called for the establishment of new industry standards and test procedures to enable a hybrid bonded chip ecosystem.

In addition to the RibbonFET, which is an improvement on the GAA process technology, Intel is developing a method of stacking multiple CMOS transistors, aiming to achieve a maximum logic scaling improvement of 30%-50% by installing more transistors per square millimeter to continue to advance Moore's Law.