EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

CYD18S72AV-100BBI

Description
Dual-Port SRAM, 256KX72, 5ns, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-484
Categorystorage    storage   
File Size628KB,25 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric Compare View All

CYD18S72AV-100BBI Overview

Dual-Port SRAM, 256KX72, 5ns, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-484

CYD18S72AV-100BBI Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerCypress Semiconductor
Parts packaging codeBGA
package instructionBGA,
Contacts484
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time5 ns
Other featuresPIPELINED ARCHITECTURE
JESD-30 codeS-PBGA-B484
JESD-609 codee0
length23 mm
memory density18874368 bit
Memory IC TypeDUAL-PORT SRAM
memory width72
Humidity sensitivity level3
Number of functions1
Number of terminals484
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX72
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
Certification statusNot Qualified
Maximum seat height1.9 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width23 mm

CYD18S72AV-100BBI Related Products

CYD18S72AV-100BBI CYD18S72AV-133BBC CYD18S72AV-100BBXI CYD18S72AV-133BBI CYD18S72AV-100BBC CYD18S72AV-133BBXC CYD18S72AV-100BBXC
Description Dual-Port SRAM, 256KX72, 5ns, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-484 Dual-Port SRAM, 256KX72, 5.5ns, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-484 Dual-Port SRAM, 256KX72, 5ns, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-484 Dual-Port SRAM, 256KX72, 5.5ns, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-484 Dual-Port SRAM, 256KX72, 5ns, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-484 Dual-Port SRAM, 256KX72, 5.5ns, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-484 Dual-Port SRAM, 256KX72, 5ns, CMOS, PBGA484, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-484
Is it lead-free? Contains lead Contains lead Lead free Contains lead Contains lead Lead free Lead free
Is it Rohs certified? incompatible incompatible conform to incompatible incompatible conform to conform to
Parts packaging code BGA BGA BGA BGA BGA BGA BGA
package instruction BGA, BGA, BGA, BGA, BGA, 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-484 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, LEAD FREE, FBGA-484
Contacts 484 484 484 484 484 484 484
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant
ECCN code 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
Maximum access time 5 ns 5.5 ns 5 ns 5.5 ns 5 ns 5.5 ns 5 ns
Other features PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE
JESD-30 code S-PBGA-B484 S-PBGA-B484 S-PBGA-B484 S-PBGA-B484 S-PBGA-B484 S-PBGA-B484 S-PBGA-B484
JESD-609 code e0 e0 e1 e0 e0 e1 e1
length 23 mm 23 mm 23 mm 23 mm 23 mm 23 mm 23 mm
memory density 18874368 bit 18874368 bit 18874368 bit 18874368 bit 18874368 bit 18874368 bit 18874368 bit
Memory IC Type DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM DUAL-PORT SRAM
memory width 72 72 72 72 72 72 72
Number of functions 1 1 1 1 1 1 1
Number of terminals 484 484 484 484 484 484 484
word count 262144 words 262144 words 262144 words 262144 words 262144 words 262144 words 262144 words
character code 256000 256000 256000 256000 256000 256000 256000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 85 °C 70 °C 85 °C 85 °C 70 °C 70 °C 70 °C
organize 256KX72 256KX72 256KX72 256KX72 256KX72 256KX72 256KX72
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code BGA BGA BGA BGA BGA BGA BGA
Package shape SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE
Package form GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) 225 225 260 225 225 260 260
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.9 mm 1.9 mm 1.9 mm 1.9 mm 1.9 mm 1.9 mm 1.9 mm
Maximum supply voltage (Vsup) 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface TIN LEAD TIN LEAD TIN SILVER COPPER TIN LEAD TIN LEAD TIN SILVER COPPER TIN SILVER COPPER
Terminal form BALL BALL BALL BALL BALL BALL BALL
Terminal pitch 1 mm 1 mm 1 mm 1 mm 1 mm 1 mm 1 mm
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
Maximum time at peak reflow temperature 30 30 20 30 30 20 20
width 23 mm 23 mm 23 mm 23 mm 23 mm 23 mm 23 mm
Maker Cypress Semiconductor Cypress Semiconductor - Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor Cypress Semiconductor
Humidity sensitivity level 3 3 - 3 3 - -
The design concept of mobile phone battery cannot be disassembled
Product design comes from demand, which either comes from customers or from market research. These two sources also determine the design concept of the product, either the product leads the industry a...
qwqwqw2088 Analogue and Mixed Signal
Help post, please tell me how to convert 7.2V power supply to 5V or 3V low power chip
Please share the low-power chip or circuit construction of 7.2V power supply to 3V or 5V, thank you all...
梦梦梦梦哲 Power technology
[Raspberry Pi 4B Review] Raspberry Pi 4 Camera Opencv and Picamera Test
[i=s]This post was last edited by lb8820265 on 2020-9-13 20:07[/i]Raspberry Pi 4 supports camera, the interface is called SCI (Camera Serial Interface). Raspberry Pi has camera accessories, using Sony...
lb8820265 Special Edition for Assessment Centres
FPGA to realize full color OLED dynamic video display control.pdf
FPGA to realize full color OLED dynamic video display control.pdf...
zxopenljx EE_FPGA Learning Park
EEWORLD University Hall----Detailed explanation of TI's mid-power audio amplifier development software PurePath Console 3
TI mid-power audio amplifier development software PurePath Console 3 detailed explanation : https://training.eeworld.com.cn/course/5658...
hi5 Talking
What should I do if I want to get an invoice after purchasing a development board from the TI store?
[font=微软雅黑][size=4]I never issued an invoice when I bought a board before, but I need one this time. I don’t know how to do it. Please advise. [/size][/font]...
littleshrimp TI Technology Forum

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号