72275L15TF datasheet, PDF - EEWORLD Datasheet

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72275L15TF: DescriptionTQFP-64, Tray; Categorystorage storage; File Size843KB，26 Pages; ManufacturerIDT (Integrated Device Technology)

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72275L15TF Overview

TQFP-64, Tray

72275L15TF Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	TQFP
package instruction	STQFP-64
Contacts	64
Manufacturer packaging code	PP64
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	10 ns
Other features	RETRANSMIT; AUTO POWER DOWN; EASY EXPANDABLE IN DEPTH AND WIDTH
Maximum clock frequency (fCLK)	66.7 MHz
period time	15 ns
JESD-30 code	S-PQFP-G64
JESD-609 code	e0
length	10 mm
memory density	589824 bit
Memory IC Type	OTHER FIFO
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	64
word count	32768 words
character code	32000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX18
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP64,.47SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.02 A
Maximum slew rate	0.09 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	10 mm

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CMOS SuperSync FIFO™

32,768 x 18

65,536 x 18

FEATURES:

•

IDT72275

IDT72285

OBSOLETE PARTS

•

Choose among the following memory organizations:

IDT72275 — 32,768 x 18

IDT72285 — 65,536 x 18

Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs

10ns read/write cycle time (6.5ns access time)

Fixed, low first word data latency time

Auto power down minimizes standby power consumption

Master Reset clears entire FIFO

Partial Reset clears data, but retains programmable

settings

Retransmit operation with fixed, low first word data

latency time

Empty, Full and Half-Full flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of two preselected offsets

Program partial flags by either serial or parallel means

Select IDT Standard timing (using

and

flags) or First

Word Fall Through timing (using

and

flags)

Output enable puts data outputs into high impedance state

Easily expandable in depth and width

Independent Read and Write Clocks (permit reading and writing

simultaneously)

Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

pin Slim Thin Quad Flat Pack (STQFP)

High-performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

FUNCTIONAL BLOCK DIAGRAM

WEN

T O

R F

A D

P E

E D

T N

E E

L M GN

O M SI

B O DE

O EC

R EW

T N

WCLK

-D

LD SEN

INPUT REGISTER

OFFSET REGISTER

WRITE CONTROL

LOGIC

FLAG

LOGIC

WRITE POINTER

RAM ARRAY

32,768 x 18

65,536 x 18

The IDT72275/72285 are exceptionally deep, high speed, CMOS First-In-

First-Out (FIFO) memories with clocked read and write controls. These FIFOs

offer numerous improvements over previous SuperSync FIFOs, including the

following:

•

The limitation of the frequency of one clock input with respect to the other has

been removed. The Frequency Select pin (FS) has been removed, thus

it is no longer necessary to select which of the two clock inputs, RCLK or

WCLK, is running at the higher frequency.

•

The period required by the retransmit operation is now fixed and short.

•

The first word data latency period, from the time the first word is written to an

empty FIFO to the time it can be read, is now fixed and short. (The variable

clock cycle counting delay associated with the latency period found on

previous SuperSync devices has been eliminated on this SuperSync family.)

DESCRIPTION:

FF/IR

PAF

EF/OR

PAE

FWFT/SI

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

-Q

4674 drw 01

AUGUST 2013

DSC-4674/6

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