UPD45D128842G5-C12-9LG datasheet, PDF

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UPD45D128842G5-C12-9LG: DescriptionIC,SDRAM,DDR,4X4MX8,CMOS,TSSOP,66PIN,PLASTIC; Categorystorage storage; File Size637KB，80 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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UPD45D128842G5-C12-9LG Overview

IC,SDRAM,DDR,4X4MX8,CMOS,TSSOP,66PIN,PLASTIC

UPD45D128842G5-C12-9LG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Renesas Electronics Corporation
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	66
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	1.5 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G66
length	22.22 mm
memory density	134217728 bit
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	66
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	MOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	10.16 mm

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD45D128442, 45D128842, 45D128164

128 M-bit Synchronous DRAM with Double Data Rate

(4-bank, SSTL_2)

Description

The

PD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic random-

access memories, organized as 8,388,608x4x4, 4194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively.

The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous

DRAM.

The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V).

The synchronous DRAM is packaged in 66-pin Plastic TSOP (II).

Features

•

Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge

•

Double Data Rate interface

Differential CLK (/CLK) input

Data inputs and DM are synchronized with both edges of DQS

Data outputs and DQS are synchronized with a cross point of CLK and /CLK

•

Quad internal banks operation

•

Possible to assert random column address in every clock cycle

•

Programmable Mode register set

/CAS latency (2, 2.5)

Burst length (2, 4, 8)

Wrap sequence (Sequential / Interleave)

•

Automatic precharge and controlled precharge

•

Auto refresh (CBR refresh) and self refresh

•

x4, x8, x16 organization

•

Byte write control (x4, x8) by DM

•

Byte write control (x16) by LDM and UDM

•

2.5 V

0.125 V Power supply for Vcc

•

2.5 V

0.125 V Power supply for VccQ

•

Maximum clock frequency up to 133 MHz

•

SSTL_2 compatible with all signals

•

4,096 refresh cycles/64 ms

•

66-pin Plastic TSOP (II) (400 mil)

•

Burst termination by Precharge command and Burst stop command

The information in this document is subject to change without notice.

Document No. M13852EJ1V1DS00 (1st edition)

Date Published December 1998 NS CP(K)

Printed in Japan

The mark

•

shows major revised points.

1998

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Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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