Digital potentiometer DS1667 with op amp

1 Introduction DS1667 contains two integrated circuit potentiometers, which can be adjusted by selecting resistive elements by counting. Each potentiometer is composed of 256 resistive elements, and each resistive segment has a tap that can be connected to a cursor. The position of the wiper in the resistor array is set by an 8-bit register, which controls which tap the wiper output is connected to. Each 8-bit register sends or receives data bits through a 3-wire serial port for read/write operations. In addition, two potentiometers connected in series can form a single potentiometer with 512 resistance segments. When the two potentiometers are used separately, the resolution of the DS1667 is equal to the resistance of the resistor divided by 256. When the potentiometers are connected in series, the resistance of the resistor is doubled, but the resolution remains unchanged. DS1667 contains two high-gain wideband operational amplifiers. Each operational amplifier has a non-inverting and inverting input terminal and an output terminal for user design and use. Operational amplifiers and potentiometers work together to complete certain functions, such as analog-to-digital conversion, digital-to-analog conversion, variable gain amplifiers, variable frequency oscillators, etc. 2 Pin arrangement and description VCC + 5V power supply GND ground L0, L1 potentiometer low-end DQ serial port input/output terminal H0, H1 potentiometer high-end CLK serial port clock input terminal W0, W1 potentiometer cursor terminal COUT cascaded serial port output terminal VB operation The negative power supply terminals of the amplifier NINV0 and NINV1. The non-inverting input terminal of the operational amplifier. SOUT. The wiper output terminals INV0 and INV1 of the stack structure. The inverting input terminal of the operational amplifier. RST. The serial port reset input terminals OUT0 and OUT1. The output terminal of the operational amplifier. 3 Main features of this digital potentiometer The main features are as follows: ·Two digitally controlled 256-bit potentiometers ·The serial port provides setting and readout methods for the two potentiometers ·Two potentiometers can be connected in series to provide additional resolution Figure 1 Pinout diagram of DS1667 2 Principle block diagram·The default position of the cursor when powered on is 1/2 of the resistor resistance·The temperature compensation of the resistor element between the two ends of the potentiometer can reach ±20%·Two high-gain broadband operational amplifiers·Low CMOS design of power consumption·Application of analog/digital conversion and digital/analog conversion, variable frequency oscillator, variable gain amplifier, etc.·20-pin dual in-line (DIP) package, 20-pin SOIC surface mount Installation·Operating temperature range: 0℃～70℃·Resistor value Resistor value resolution -3dB point DS1667-1010Ω39Ω1.1MHz DS1667-5050Ω195Ω200.0kHz DS1667-100100Ω390Ω100.0kHz 4 Working principle of the digital potentiometer part The schematic block diagram of the digital potentiometer part of DS1667 is shown in Figure 2. As can be seen from Figure 2, DS1667 contains two potentiometers, each potentiometer has its own cursor, which is set by a value contained in an 8-bit register. Each potentiometer consists of 256 resistors of equal resistance, connected by taps to each other and to the last resistor. In addition, the potentiometers can be stacked in series, that is, the high end of potentiometer 0 is connected to the low end of potentiometer 1. As a stack potentiometer, the stack select bit is used to select which potentiometer's wiper will appear in the multiple output terminal SOUT. If 0 is written to the stack demultiplexer, wiper 0 will be connected to the SOUT pin. This wiper will determine which bit to select from the 256 taps at the bottom of the stack potentiometer. If a 1 is written into the stack demultiplexer, wiper 1 is selected and one of the 256 taps in the upper part of the stack potentiometer is connected to the SOUT pin. Through the 17-bit I/O shift register, data can be read from or written to the wiper 0 and wiper 1 registers and the stack select bits. The I/O shift register is a 3-wire serial port load, and the 3-wire serial port consists of RST, DQ and CLK. It modifies the data by transmitting 17 bits. Serial writing of data through the DQ pin is only allowed when the RST input is high. Before the RST terminal becomes low level, the potentiometer always maintains its previous value. When RST becomes low level, the value of the potentiometer will change. When RST input is low level, DQ and CLK inputs have no effect. When RST is high, the CLK input changes from low to high, and valid data is written into the I/O shift register. Regardless of whether the clock input is high level or low level, the input data of the DQ pin can be changed, and only when the setting requirements are met, the value of the DQ pin is sent to the shift register. Data writing always starts with the value of the stack select bit. The next 8 bits sent in specify the cursor setting value of potentiometer 1. The most significant bit of these 8 bits of data is sent first. The next 8 bits specify the cursor setting value of potentiometer 0. The most significant bit is sent out first. Most significant bit. The 17th bit of data sent in is the least significant bit set by cursor 0. If the data written is less than 17 digits, the value set by the potentiometer will be the data written plus the previously unconverted reserved bits. If the data written is greater than 17 bits, the last 17 bits of data remain in the shift register. Therefore, if the data sent is not 17 bits, the potentiometer setting will be inaccurate. When multiple bits of data are written into the shift register, the previous data is shifted out bit by bit through the cascaded serial port pin COUT. By connecting the COUT of one DS1667 to the DQ pin of another DS1667, multiple potentiometers can act like a chain. They are connected in series as shown in Figure 3.