PCA9672
Remote 8-bit I/O expander for Fm+ I
2
C-bus with interrupt and
reset
Rev. 02 — 6 July 2007
Product data sheet
1. General description
The PCA9672 provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional bus (I
2
C-bus) and is a part of the Fast-mode Plus
family.
The PCA9672 is a drop-in upgrade for the PCF8574 providing higher Fast-mode Plus
(Fm+) I
2
C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM
dimming of LEDs, higher I
2
C-bus drive (30 mA versus 3 mA) so that many more devices
can be on the bus without the need for bus buffers, higher total package sink capacity
(200 mA versus 100 mA) that supports having all LEDs on at the same time and more
device addresses (16 versus 8) are available to allow many more devices on the bus
without address conflicts.
The difference between the PCA9672 and the PCF8574 is that the A2 address pin is
replaced by the RESET input on the PCA9672.
The device consists of an 8-bit quasi-bidirectional port and an I
2
C-bus interface. The
PCA9672 has low current consumption and include latched outputs with 25 mA high
current drive capability for directly driving LEDs.
The PCA9672 possesses an interrupt line (INT) that can be connected to the interrupt
logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can
inform the microcontroller if there is incoming data on its ports without having to
communicate via the I
2
C-bus.
The internal Power-On Reset (POR), hardware reset pin (RESET), or Software Reset
sequence initializes the I/Os as inputs.
2. Features
I
I
I
I
I
I
I
I
I
I
1 MHz I
2
C-bus interface
Compliant with the I
2
C-bus Fast and Standard modes
SDA with 30 mA sink capability for 4000 pF buses
2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
8-bit remote I/O pins that default to inputs at power-up
Latched outputs with 25 mA sink capability for directly driving LEDs
Total package sink capability of 200 mA
Active LOW open-drain interrupt output
16 programmable slave addresses using 2 address pins
Readable device ID (manufacturer, device type, and revision)
NXP Semiconductors
PCA9672
Remote 8-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
I
Low standby current
I
−40 °C
to +85
°C
operation
I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
I
Packages offered: SO16, TSSOP16, HVQFN16
3. Applications
I
I
I
I
I
I
I
I
LED signs and displays
Servers
Industrial control
Medical equipment
PLCs
Cellular telephones
Gaming machines
Instrumentation and test measurement
4. Ordering information
Table 1.
Type
number
PCA9672BS
Ordering information
Topside
mark
672
Package
Name
HVQFN16
Description
plastic thermal enhanced very thin quad
flat package; no leads; 16 terminals;
body 3
×
3
×
0.85 mm
plastic small outline package; 16 leads;
body width 7.5 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT758-1
PCA9672D
PCA9672D SO16
TSSOP16
SOT162-1
SOT403-1
PCA9672PW PCA9672
PCA9672_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 6 July 2007
2 of 27
NXP Semiconductors
PCA9672
Remote 8-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
5. Block diagram
PCA9672
INT
AD0
AD1
INTERRUPT
LOGIC
LP FILTER
SCL
SDA
INPUT
FILTER
I
2
C-BUS
CONTROL
SHIFT
REGISTER
8 BITS
I/O
PORT
P0 to P7
RESET
V
DD
V
SS
POWER-ON
RESET
write pulse
read pulse
002aac321
Fig 1. Block diagram of PCA9672
write pulse
I
trt(pu)
data from Shift Register
D
FF
CI
S
power-on reset
D
FF
read pulse
CI
S
Q
Q
100
µA
I
OH
V
DD
I
OL
P0 to P7
V
SS
data to Shift Register
002aac109
to interrupt logic
Fig 2. Simplified schematic diagram of P0 to P7
PCA9672_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 6 July 2007
3 of 27
NXP Semiconductors
PCA9672
Remote 8-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
6. Pinning information
6.1 Pinning
AD0
AD1
RESET
P0
P1
P2
P3
V
SS
1
2
3
4
5
6
7
8
002aac322
16 V
DD
15 SDA
14 SCL
13 INT
12 P7
11 P6
10 P5
9
P4
AD0
AD1
RESET
P0
P1
P2
P3
V
SS
1
2
3
4
5
6
7
8
002aac323
16 V
DD
15 SDA
14 SCL
13 INT
12 P7
11 P6
10 P5
9
P4
PCA9672D
PCA9672PW
Fig 3. Pin configuration for SO16
16 AD1
15 AD0
terminal 1
index area
Fig 4. Pin configuration for TSSOP16
13 SDA
12 SCL
11 INT
10 P7
9
5
6
7
8
P6
P5
14 V
DD
P4
RESET
P0
P1
P2
1
2
PCA9672BS
3
4
P3
V
SS
002aac325
Transparent top view
Fig 5. Pin configuration for HVQFN16
6.2 Pin description
Table 2.
Symbol
AD0
AD1
RESET
P0
P1
P2
P3
V
SS
P4
P5
P6
PCA9672_2
Pin description
Pin
SO16, TSSOP16
1
2
3
4
5
6
7
8
9
10
11
HVQFN16
15
16
1
2
3
4
5
6
[1]
7
8
9
address input 0
address input 1
reset input (active LOW)
quasi-bidirectional I/O 0
quasi-bidirectional I/O 1
quasi-bidirectional I/O 2
quasi-bidirectional I/O 3
supply ground
quasi-bidirectional I/O 4
quasi-bidirectional I/O 5
quasi-bidirectional I/O 6
© NXP B.V. 2007. All rights reserved.
Description
Product data sheet
Rev. 02 — 6 July 2007
4 of 27
NXP Semiconductors
PCA9672
Remote 8-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
Pin description
…continued
Pin
SO16, TSSOP16
HVQFN16
10
11
12
13
14
quasi-bidirectional I/O 7
interrupt output (active LOW)
serial clock line
serial data line
supply voltage
12
13
14
15
16
Description
Table 2.
Symbol
P7
INT
SCL
SDA
V
DD
[1]
HVQFN package die supply ground is connected to both the V
SS
pin and the exposed center pad. The V
SS
pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
7. Functional description
Refer to
Figure 1 “Block diagram of PCA9672”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9672 is shown in
Figure 6.
Slave address pins AD1 and AD0 choose 1 of 16 slave
addresses. To conserve power, no internal pull-up resistors are incorporated on AD1 and
AD0. Address values depending on AD1 and AD0 can be found in
Table 3 “PCA9672
address map”.
Remark:
When using the PCA9672 reserved I
2
C-bus addresses must be used with
caution since they can interfere with:
•
“reserved for future use” I
2
C-bus addresses (0000 011, 1111 101, 1111 110,
1111 111)
•
slave devices that use the 10-bit addressing scheme (1111 0xx)
•
High speed mode (Hs-mode) master code (0000 1xx)
slave address
A6
A5
A4
A3
A2
A1
A0 R/W
programmable
002aab636
Fig 6. PCA9672 address
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation.
When AD1 and AD0 are held to V
DD
or V
SS
, the same address as the PCF8574 with A2
held to V
SS
is applied.
PCA9672_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 6 July 2007
5 of 27
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