5P49V5943BDDDNDGI datasheet, PDF

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5P49V5943BDDDNDGI: DescriptionProcessor Specific Clock Generator, 350MHz, CMOS, 3 X 3 MM, 0.40 MM PITCH, ROHS COMPLIANT, MO-220, VFQFPN-20; CategoryThe embedded processor and controller Microcontrollers and processors; File Size410KB，33 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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5P49V5943BDDDNDGI Overview

Processor Specific Clock Generator, 350MHz, CMOS, 3 X 3 MM, 0.40 MM PITCH, ROHS COMPLIANT, MO-220, VFQFPN-20

5P49V5943BDDDNDGI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
package instruction	HVQCCN,
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	IT ALSO OPREATES AT 2.5V AND 3.3V NOMINAL SUPPLY
JESD-30 code	S-XQCC-N20
length	3 mm
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	350 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Master clock/crystal nominal frequency	350 MHz
Maximum seat height	1 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.4 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

5P49V5943BDDDNDGI Preview

Programmable Clock Generator

5P49V5943

DATASHEET

Description

The 5P49V5943 is a programmable clock generator intended

for high performance consumer, networking, industrial,

computing, and data-communications applications.

Configurations may be stored in on-chip One-Time

Programmable (OTP) memory or changed using I

interface. This is IDTs fifth generation of programmable clock

technology (VersaClock

5).

The frequencies are generated from a single input reference

clock.

Two select pins allow up to 4 different configurations to be

programmed and accessible using processor GPIOs or

bootstrapping. The different selections may be used for

different operating modes (full function, partial function, partial

power-down), regional standards (US, Japan, Europe) or

system production margin testing.

The device may be configured to use one of two I

addresses to allow multiple devices to be used in a system.

Features

•

Generates up to two independent output frequencies

•

High performance, low phase noise PLL, <0.7 ps RMS

typical phase jitter on outputs:

– PCIe Gen1, 2, 3 compliant clock capability

– USB 3.0 compliant clock capability

– 1 GbE and 10 GbE

•

Two fractional output dividers (FODs)

•

Independent Spread Spectrum capability on each output

pair

•

Four banks of internal non-volatile in-system

programmable or factory programmable OTP memory

•

C serial programming interface

•

One reference LVCMOS output clock

•

Two universal output pairs:

– Each configurable as one differential output pair or two

LVCMOS outputs

I/O Standards:

– Single-ended I/Os: 1.8V to 3.3V LVCMOS

– Differential I/Os - LVPECL, LVDS and HCSL

Pin Assignment

OUT0_SEL_I2CB

•

Input frequency ranges:

DDO

GND

DDD

– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,

CLKINB) – 1MHz to 350MHz

Output frequency ranges:

– LVCMOS Clock Outputs – 1MHz to 200MHz

– LVDS, LVPECL, HCSL Differential Clock Outputs –

1MHz to 350MHz

•

CLKIN

CLKINB

DDA

SD/OE

20 19 18 17 16

DDO

OUT1

OUT1B

GND

•

Individually selectable output voltage (1.8V, 2.5V, 3.3V) for

each output pair

EPAD

•

Programmable loop bandwidth

Programmable output to output skew

Programmable slew rate control

Individual output enable/disable

Power-down mode

1.8V, 2.5V or 3.3V core V

DDD

, V

DDA

Available in 20-pin VFQFPN 3mm x 3mm package

-40° to +85°C industrial temperature operation

SEL1/SDA

SEL0/SCL

DDO

OUT2

20-pin VFQFPN

5P49V5943 MARCH 3, 2017

OUT2B

5P49V5943 DATASHEET

Functional Block Diagram

CLKIN

CLKINB

DDO

PLL

OTP

and

Control Logic

DDO

OUT0_SEL_I2CB

SD/OE

SEL1/SDA

SEL0/SCL

DDA

DDD

FOD2

FOD1

OUT1

OUT1B

DDO

OUT2

OUT2B

Applications

•

Ethernet switch/router

PCI Express 1.0/2.0/3.0

Broadcast video/audio timing

Multi-function printer

Processor and FPGA clocking

Any-frequency clock conversion

MSAN/DSLAM/PON

Fiber Channel, SAN

Telecom line cards

1 GbE and 10 GbE

PROGRAMMABLE CLOCK GENERATOR

MARCH 3, 2017

5P49V5943 DATASHEET

Table 1: Pin Descriptions

Number

Name

CLKIN

CLKINB

VDDA

VDD

Input

Power

Type

Pull-down

Description

Differential clock input. Weak 100kohms internal pull-down.

Complementary differential clock input. Weak 100kohms internal pull-down.

Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD

should have the same voltage applied.

Power supply pin. Connect to 1.8 to 3.3V.

Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit

controls the configuration of the SD/OE pin. The SH bit needs to be high for

SD/OE pin to be configured as SD. The SP bit (0x02) controls the polarity of the

signal to be either active HIGH or LOW only when pin is configured as OE

(Default is active LOW.) Weak internal pull down resistor. When configured as

SD, device is shut down, differential outputs are driven high/low, and the single-

ended LVCMOS outputs are driven low. When configured as OE, and outputs are

disabled, the outputs can be selected to be tri-stated or driven high/low,

depending on the programming bits as shown in the SD/OE Pin Function Truth

table.

Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB.

Weak internal pull down resistor.

Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB.

Weak internal pull down resistor.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT2/OUT2B.

Output Clock 2. Please refer to the Output Drivers section for more details.

Complementary Output Clock 2. Please refer to the Output Drivers section for

more details.

Connect to ground.

Complementary Output Clock 1. Please refer to the Output Drivers section for

more details.

Output Clock 1. Please refer to the Output Drivers section for more details.

Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for

OUT1/OUT1B.

Connect to ground.

Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDB

should have the same voltage applied.

Connect to ground.

Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output

voltage levels for OUT0.

Latched input/LVCMOS Output. At power up, the voltage at the pin

OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8

and 9. If a weak pull up (10Kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9

will be configured as hardware select pins, SEL1 and SEL0. If a weak pull down

(10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will

act as the SDA and SCL pins of an I2C interface. After power up, the pin acts as

a LVCMOS reference output.

Connect to ground pad.

SD/OE

Input

Pull-down

SEL1/SDA

SEL0/SCL

VDDO2

OUT2

OUT2B

GND

OUT1B

OUT1

VDDO1

GND

VDDD

GND

VDDO0

Input

Power

Output

Power

Output

Power

Pull-down

OUT0_SELB_I2C Input/Output

Pull-down

ePAD

Power

MARCH 3, 2017

PROGRAMMABLE CLOCK GENERATOR

5P49V5943 DATASHEET

PLL Features and Descriptions

Spread Spectrum

To help reduce electromagnetic interference (EMI), the

5P49V5943 supports spread spectrum modulation. The

output clock frequencies can be modulated to spread energy

across a broader range of frequencies, lowering system EMI.

The 5P49V5943 implements spread spectrum using the

Fractional-N output divide, to achieve controllable modulation

rate and spreading magnitude. The Spread spectrum can be

applied to any output clock, any clock frequency, and any

spread amount from ±0.25% to ±2.5% center spread and

-0.5% to -5% down spread.

After a pin level change, the device must not be interrupted for

at least 1ms so that the new values have time to load and take

effect.

If OUT0_SEL_I2CB was 0 at POR, alternate configurations

can only be loaded via the I2C interface.

Table 2:

Loop Filter

PLL loop bandwidth range depends on the input reference

frequency (Fref) and can be set between the loop bandwidth

range as shown in the table below.

Input Reference

Loop

Frequency–Fref Bandwidth Min Bandwidth Max

(MHz)

(kHz)

350

300

126

1000

Table 3:

Configuration Table

This table shows the SEL1, SEL0 settings to select the

configuration stored in OTP. Four configurations can be stored

in OTP. These can be factory programmed or user

programmed.

OUT0_SEL_I2CB SEL1 SEL0

REG0:7 Config

@ POR

Access

Yes

I2C

defaults

At power up time, the SEL0 and SEL1 pins must be tied to

either the VDDD/VDDA power supply so that they ramp with

that supply or are tied low (this is the same as floating the

pins). This will cause the register configuration to be loaded

that is selected according to Table 3 above. Providing that

OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after

the first 10mS of operation the levels of the SELx pins can be

changed, either to low or to the same level as VDDD/VDDA.

The SELx pins must be driven with a digital signal of < 300ns

Rise/Fall time and only a single pin can be changed at a time.

PROGRAMMABLE CLOCK GENERATOR

MARCH 3, 2017

5P49V5943 DATASHEET

Reference Clock Input Pins

The 5P49V5943 supports one reference clock input. The

clock input (CLKIN, CLKINB) is a fully differential input that

only accepts a reference clock. The differential input accepts

differential clocks from all the differential logic types and can

also be driven from a single ended clock on one of the input

pins.

outputs are driven High/low, and the single-ended LVCMOS

outputs are driven low. When configured as OE, and outputs

are disabled, the outputs are driven high/low.

Table 4:

SD/OE Pin Function Truth Table

OUTn

Tri-state

Output active

Output driven High Low

Tri-state

Output active

Output driven High Low

Output active

Tri-state

Output active

Tri-state

Output active

Output driven High Low

SH bit SP bit OSn bit OEn bit SD/OE

OTP Interface

The 5P49V5943 can also store its configuration in an internal

OTP. The contents of the device's internal programming

registers can be saved to the OTP by setting burn_start

(W114[3]) to high and can be loaded back to the internal

programming registers by setting usr_rd_start(W114[0]) to

high.

To initiate a save or restore using I

C, only two bytes are

transferred. The Device Address is issued with the read/write

bit set to “0”, followed by the appropriate command code. The

save or restore instruction executes after the STOP condition

is issued by the Master, during which time the 5P49V5943 will

not generate Acknowledge bits. The 5P49V5943 will

acknowledge the instructions after it has completed execution

of them. During that time, the I

C bus should be interpreted as

busy by all other users of the bus.

On power-up of the 5P49V5943, an automatic restore is

performed to load the OTP contents into the internal

programming registers. The 5P49V5943 will be ready to

accept a programming instruction once it acknowledges its

7-bit I

C address.

Availability of Primary and Secondary I

C addresses to allow

programming for multiple devices in a system. The I

C slave

address can be changed from the default 0xD4 to 0xD0 by

programming the I2C_ADDR bit D0.

VersaClock 5

Programming Guide

provides detailed I

C programming

guidelines and register map.

Note 1 : Global Shutdown

Note 2 : Tri-state regardless of OEn bits

Output Alignment

Each output divider block has a synchronizing POR pulse to

provide startup alignment between outputs. This allows

alignment of outputs for low skew performance. The phase

alignment works both for integer output divider values and for

fractional output divider values.

Besides the POR at power up, the same synchronization reset

is also triggered when switching between configurations with

the SEL0/1 pins. This ensures that the outputs remain aligned

in every configuration. This reset causes the outputs to

suspend for a few hundred microseconds so the switchover is

not glitch-less. The reset can be disabled for applications

where glitch-less switch over is required and alignment is not

critical.

When using I

C to reprogram an output divider during

operation, alignment can be lost. Alignment can be restored

by manually triggering the reset through I

When alignment is required for outputs with different

frequencies, the outputs are actually aligned on the falling

edges of each output by default. Rising edge alignment can

also be achieved by utilizing the programmable skew feature

to delay the faster clock by 180 degrees. The programmable

skew feature also allows for fine tuning of the alignment.

For details of register programming, please see

VersaClock 5

Family Register Descriptions and Programming Guide

for

details.

SD/OE Pin Function

The polarity of the SD/OE signal pin can be programmed to be

either active HIGH or LOW with the SP bit (W16[1]). When SP

is “0” (default), the pin becomes active LOW and when SP is

“1”, the pin becomes active HIGH. The SD/OE pin can be

configured as either to shutdown the PLL or to enable/disable

the outputs. The SH bit controls the configuration of the

SD/OE pin The SH bit needs to be high for SD/OE pin to be

configured as SD

SD/OE Input

OEn

Global Shutdown

OSn

OUTn

When configured as SD, device is shut down, differential

MARCH 3, 2017

PROGRAMMABLE CLOCK GENERATOR

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5P49V5943BDDDNDGI Related Products

	5P49V5943BDDDNDGI	5P49V5943BDDDNDGI8
Description	Processor Specific Clock Generator, 350MHz, CMOS, 3 X 3 MM, 0.40 MM PITCH, ROHS COMPLIANT, MO-220, VFQFPN-20	Processor Specific Clock Generator, 350MHz, CMOS, 3 X 3 MM, 0.40 MM PITCH, ROHS COMPLIANT, MO-220, VFQFPN-20
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
package instruction	HVQCCN,	HVQCCN,
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
Other features	IT ALSO OPREATES AT 2.5V AND 3.3V NOMINAL SUPPLY	IT ALSO OPREATES AT 2.5V AND 3.3V NOMINAL SUPPLY
JESD-30 code	S-XQCC-N20	S-XQCC-N20
length	3 mm	3 mm
Number of terminals	20	20
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Maximum output clock frequency	350 MHz	350 MHz
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
Master clock/crystal nominal frequency	350 MHz	350 MHz
Maximum seat height	1 mm	1 mm
Maximum supply voltage	3.465 V	3.465 V
Minimum supply voltage	1.71 V	1.71 V
Nominal supply voltage	1.8 V	1.8 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.4 mm	0.4 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	3 mm	3 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC

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