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MSM8512VI-70

Description
Standard SRAM, 512KX8, 70ns, CMOS, CDXA32, 0.100 INCH, CERAMIC, VIL-32
Categorystorage    storage   
File Size60KB,8 Pages
ManufacturerAPTA Group Inc
Download Datasheet Parametric View All

MSM8512VI-70 Overview

Standard SRAM, 512KX8, 70ns, CMOS, CDXA32, 0.100 INCH, CERAMIC, VIL-32

MSM8512VI-70 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerAPTA Group Inc
Parts packaging codeVIL
package instructionDIP, DIP32,.1
Contacts32
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-CDXA-T32
JESD-609 codee0
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize512KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP32,.1
Package shapeRECTANGULAR
Package formVERTICAL IN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum standby current0.003 A
Minimum standby current4.5 V
Maximum slew rate0.07 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE
512K x 8 SRAM
MSM8512 - 70/85/10
Issue 4.5 : April 2001
Description
The MSM8512 is a 4Mbit monolithic SRAM
organised as 512K x 8 with access times from
70ns to 100ns available. The device is available in
a 32 pin ceramic space saving VIL
TM
. The device
has a low power standby version which supports
data retention mode and is directly TTL compatible.
All versions can be screened in accordance with
MIL-STD-883C.
524,288 x 8 CMOS Static RAM
Features
Fast Access Times of 70/85/100 ns
Average Operating Power
425 mW (max)
Standby Power
635
µW
(max) -L version
Low voltage data retention.
Completely Static Operation
Directly TTL compatible
May be processed in accordance with MIL-STD-883C
Block Diagram
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
D0
D7
WE
OE
CS
Pin Definition
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
4,194,304
BIT
MEMORY
ARRAY
S,V
Package
Top View
26
25
24
23
22
21
20
19
18
17
I/O
BUFFER
COLUMN I/O
COLUMN DECODE
Y ADDRESS BUFFER
A8
A7
A6
A5
A4
A3
A2
A1
A0
Vcc
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
X ADDRESS BUFFER
ROW DECODE
Package Details
Pin Count
32
Descripion
0.1" Vertical-in-line (VIL
TM
)
Package Type
V
Pin Functions
A0-A18
Address Inputs
D0-7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
Power (+5V)
V
CC
GND
Ground
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