W49F002UP90 datasheet, PDF - EEWORLD Datasheet

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W49F002UP90: DescriptionFlash, 256KX8, 90ns, PQCC32, PLASTIC, LCC-32; Categorystorage storage; File Size304KB，23 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W49F002UP90 Overview

Flash, 256KX8, 90ns, PQCC32, PLASTIC, LCC-32

W49F002UP90 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Winbond Electronics Corporation
Parts packaging code	QFJ
package instruction	PLASTIC, LCC-32
Contacts	32
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	90 ns
startup block	BOTTOM
JESD-30 code	R-PQCC-J32
JESD-609 code	e0
length	13.97 mm
memory density	2097152 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	32
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	3.56 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
type	NOR TYPE
width	11.43 mm

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W49F002U

256K

8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K

8 bits. The

device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V

not required. The unique cell architecture of the W49F002U results in fast program/erase operations

with extremely low current consumption (compared to other comparable 5-volt flash memory

products). The device can also be programmed and erased using standard EPROM programmers.

FEATURES

•

Single 5-volt operations:

−

5-volt Read

−

5-volt Erase

−

5-volt Program

Fast Program operation:

−

Byte-by-Byte programming: 35

µS

(typ.)

Fast Erase operation: 100 mS (typ.)

Fast Read access time: 70/90/120 nS

Endurance: 10K cycles (typ.)

Ten-year data retention

Hardware data protection

One 16K byte Boot Block with Lockout

protection

Two 8K byte Parameter Blocks

•

Two Main Memory Blocks (96K, 128K) Bytes

Low power consumption

−

Active current: 25 mA (typ.)

−

Standby current: 20

µA

(typ.)

•

Automatic program and erase timing with

internal V

generation

End of program or erase detection

−

Toggle bit

−

Data polling

•

Latched address and data

TTL compatible I/O

JEDEC standard byte-wide pinouts

Available packages: 32-pin DIP and 32-pin

TSOP and 32-pin-PLCC

-1-

Publication Release Date: April 2000

Revision A2

W49F002U

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W49F002U is controlled by CE and OE, both of which have to be low for

the host to obtain data from the outputs.

is used for device selection. When

is high, the chip

is de-selected and only standby power will be consumed. OE is the output control and is used to gate

data from the output pins. The data bus is in high impedance state when either

is high.

Refer to the timing waveforms for further details.

Reset Operation

The reset input pin can be used in some application. When RESET pin is at high state, the device is

in normal operation mode. When RESET pin is at low state, it will halts the device and all outputs are

at high impedance state. As the high state re-asserted to the RESET pin, the device will return to

read or standby mode, it depends on the control signals. When the system drives the RESET pin low

for at least a period of 500 nS, the device immediately terminates any operation in progress duration

of the RESET pulse. The other function for RESET pin is temporary reset the boot block. By

applying the 12V to RESET pin, the boot block can be reprogrammed even though the boot block

lockout function is enabled.

Boot Block Operation

There is one 16K-byte boot block in this device, which can be used to store boot code. It is located in

the last 16K bytes with the address range of the boot block is 3C000(hex) to 3FFFF(hex).See

Command Code sequence for Boot Block Lockout Enable for the specific code. Once this feature is

set the data for the designated block cannot be erased or programmed (programming lockout); other

memory locations can be changed with the regular programming method. Once the boot block

programming lockout feature is activated, the chip erase function can no longer erase the boot block.

There is one condition that the lockout feature can be overridden. Just apply 12V to RESET pin, the

lockout feature will temporarily be inactivated and the block can be erased/programmed. Once the

RESET pin return to TTL level, the lockout feature will be activated again.

In order to detect whether the boot block feature is set on the 16K-bytes block, users can perform

software command code sequence: enter the product identification mode (see Command Codes for

Identification/Boot Block Lockout Detection for specific code), and then read from address "0002

(hex)". If the DQ

of output data is "1," the boot block programming lockout feature is activated; if the

DQ0

output data is "0 ," the lockout feature is inactivated and the block can be

erased/programmed.

To return to normal operation, perform a three-byte command code sequence (or an alternate single-

byte command) to exit the identification mode. For the specific code, see Command Code for

Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-byte command code sequence. After the command

loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be

completed as fast as 100 mS (typical). The host system is not required to provide any control or

timing during this operation. The entire memory array will be erased to FF hex. by the chip erase

Publication Release Date: April 2000

Revision A2

-3-

W49F002U

operation if the boot block programming lockout feature is not activated. Once the boot block lockout

feature is activated, the whole chip erase function will erase the two main memory blocks and the two

parameter blocks but not the boot block. The device will automatically return to normal read mode

after the erase operation. Data polling and/or Toggle Bits can be used to detect end of erase cycle.

Sector Erase Operation

There are four sectors: two main memory blocks and two parameters blocks which can be erased

individually by initiating a six-byte command code sequence. Sector address is latched on the falling

edge of

signal in the sixth cycle while the data input "30(hex)" is latched at the rising edge of

in this cycle. After the command loading cycle, the device enters the internal sector erase mode,

which is automatically timed and will be completed as fast as 100 mS (typical). The host system does

not require to provide any control or timing during this operation. The device will automatically return

to normal read mode after the erase operation. Data polling and/or Toggle Bits can be used to detect

the end of erase cycle.

When different sector address is loaded in the sixth cycle for sector erase command, the

correspondent sectors will be erased automatically; that these sections will be erased independedntly.

For detail sector to be erased information, please refer to the

Table of Command Definition.

Program Operation

The W49F002U is programmed on a byte-by-byte basis. Program operation can only change logical

data "1" to logical data "0". The erase operation (changed entire data in two main memory blocks and

two parameter blocks and/or boot block from "0" to "1") is needed before programming.

The program operation is initiated by a 4-byte command code sequence (see Command Codes for

Byte Programming). The device will internally enter the program operation immediately after the byte-

program command is entered. The internal program timer will automatically time-out (50

µS

max. -

). Once completed, the device returns to normal read mode. Data polling and/or Toggle Bits can

be used to detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W49F002U is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A

pulse of less than 15 nS in duration will not initiate a write cycle.

(2) V

Power Up/Down Detection: The programming operation is inhibited when V

is less than

2.5V typical.

(3) Write Inhibit Mode: Forcing

low,

high, or

high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) V

power-on delay: When V

has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Data Polling (DQ

)- Write Status Detection

The W49F002U includes a data polling feature to indicate the end of a program or erase cycle.

When the W49F002U is in the internal program or erase cycle, any attempt to read DQ

of the last

byte loaded will receive the complement of the true data. Once the program or erase cycle is

completed, DQ

will show the true data. Note that DQ

will show logical "0" during the erase cycle,

and become logical "1" or true data when the erase cycle has been completed.

-4-

W49F002UP90 Related Products

	W49F002UP90	W49F002U-12	W49F002UT70	W49F002UT12	W49F002U-70	W49F002UP12	W49F002UT90	W49F002U-90	W49F002UP70
Description	Flash, 256KX8, 90ns, PQCC32, PLASTIC, LCC-32	Flash, 256KX8, 120ns, PDIP32, PLASTIC, DIP-32	Flash, 256KX8, 70ns, PDSO32, 8 X 20 MM, TSOP-32	Flash, 256KX8, 120ns, PDSO32, 8 X 20 MM, TSOP-32	Flash, 256KX8, 70ns, PDIP32, PLASTIC, DIP-32	Flash, 256KX8, 120ns, PQCC32, PLASTIC, LCC-32	Flash, 256KX8, 90ns, PDSO32, 8 X 20 MM, TSOP-32	Flash, 256KX8, 90ns, PDIP32, PLASTIC, DIP-32	Flash, 256KX8, 70ns, PQCC32, PLASTIC, LCC-32
Parts packaging code	QFJ	DIP	TSOP	TSOP	DIP	QFJ	TSOP	DIP	QFJ
package instruction	PLASTIC, LCC-32	PLASTIC, DIP-32	8 X 20 MM, TSOP-32	8 X 20 MM, TSOP-32	PLASTIC, DIP-32	PLASTIC, LCC-32	8 X 20 MM, TSOP-32	PLASTIC, DIP-32	PLASTIC, LCC-32
Contacts	32	32	32	32	32	32	32	32	32
Reach Compliance Code	compliant	unknown	unknown	unknown	compliant	unknown	compliant	compliant	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Maximum access time	90 ns	120 ns	70 ns	120 ns	70 ns	120 ns	90 ns	90 ns	70 ns
startup block	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
JESD-30 code	R-PQCC-J32	R-PDIP-T32	R-PDSO-G32	R-PDSO-G32	R-PDIP-T32	R-PQCC-J32	R-PDSO-G32	R-PDIP-T32	R-PQCC-J32
length	13.97 mm	41.91 mm	18.4 mm	18.4 mm	41.91 mm	13.97 mm	18.4 mm	41.91 mm	13.97 mm
memory density	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit	2097152 bit
Memory IC Type	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH
memory width	8	8	8	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1	1	1	1
Number of terminals	32	32	32	32	32	32	32	32	32
word count	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words	262144 words
character code	256000	256000	256000	256000	256000	256000	256000	256000	256000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	256KX8	256KX8	256KX8	256KX8	256KX8	256KX8	256KX8	256KX8	256KX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	DIP	TSOP1	TSOP1	DIP	QCCJ	TSOP1	DIP	QCCJ
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER	IN-LINE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	IN-LINE	CHIP CARRIER	SMALL OUTLINE, THIN PROFILE	IN-LINE	CHIP CARRIER
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Programming voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.56 mm	5.33 mm	1.2 mm	1.2 mm	5.33 mm	3.56 mm	1.2 mm	5.33 mm	3.56 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	NO	YES	YES	NO	YES	YES	NO	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	J BEND	THROUGH-HOLE	GULL WING	GULL WING	THROUGH-HOLE	J BEND	GULL WING	THROUGH-HOLE	J BEND
Terminal pitch	1.27 mm	2.54 mm	0.5 mm	0.5 mm	2.54 mm	1.27 mm	0.5 mm	2.54 mm	1.27 mm
Terminal location	QUAD	DUAL	DUAL	DUAL	DUAL	QUAD	DUAL	DUAL	QUAD
type	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE
width	11.43 mm	15.24 mm	8 mm	8 mm	15.24 mm	11.43 mm	8 mm	15.24 mm	11.43 mm
Is it Rohs certified?	incompatible	incompatible	incompatible	-	incompatible	-	incompatible	incompatible	incompatible
Maker	Winbond Electronics Corporation	-	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation
JESD-609 code	e0	e0	e0	-	e0	-	e0	e0	e0
Peak Reflow Temperature (Celsius)	225	NOT SPECIFIED	240	-	NOT SPECIFIED	-	240	NOT SPECIFIED	225
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	-	TIN LEAD	-	TIN LEAD	TIN LEAD	TIN LEAD
Maximum time at peak reflow temperature	30	NOT SPECIFIED	30	-	NOT SPECIFIED	-	30	NOT SPECIFIED	30

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