STAC9752AXTAEYYXR datasheet, PDF

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STAC9752AXTAEYYXR: DescriptionPCM Codec, 1-Func, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-48; CategoryWireless rf/communication Telecom circuit; File Size625KB，106 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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STAC9752AXTAEYYXR Overview

PCM Codec, 1-Func, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-48

STAC9752AXTAEYYXR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-48
Contacts	48
Reach Compliance Code	compliant
Other features	ALSO REQUIRES 5 V ANALOG SUPPLY
filter	YES
JESD-30 code	S-PQFP-G48
JESD-609 code	e3
length	7 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	48
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.6 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	PCM CODEC
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	7 mm

STAC9752AXTAEYYXR Preview

DATASHEET

AC’97 2.3 CODECS WITH STEREO

MICROPHONE & UNIVERSAL JACK

FEATURES

•

High Performance

Σ∆

Technology

AC’97 Rev 2.3 Complaint

20-bit Full Duplex Stereo ADC & DACs

Independent Sample Rates for ADC & DACs

5-Wire AC-Link Protocol Compliance

20-Bit SPDIF Output

Universal Jacks

™

Full Stereo Microphone Pre-Amp

Internal Jack Sensing on Headphone & Line_Out

Internal Microphone Input Sensing

Digital PC Beep Option

Extended AC’97 2.3 Paging Registers

General Purpose I/Os and Crystal Elimination

Circuit

Headphone Drive Capability (50 mW per channel)

Switchable Headphone Out (pins 39/41 or 35/36)

0dB, 10dB, 20dB and 30dB Microphone Boost

Capability

+3.3 V (STAC9753A) and +5 V (STAC9752A) Analog

Power Supply Options

Pin Compatible with STAC9750/52/66

•

Reference Designs

STAC9752A/9753A

DESCRIPTION

IDT's STAC9752A/9753A are general purpose 20-bit, full

duplex, audio CODECs conforming to the analog compo-

nent specification of AC'97 (Audio CODEC 97 Component

Specification Rev. 2.3). The STAC9752A/9753A incorpo-

rates IDT's proprietary

Σ∆

technology.

The AC’97 CODEC is designed to achieve a DAC SNR in

excess of 94dB. The DACs, ADCs, and mixer are inte-

grated with analog I/Os, which include four analog

line-level stereo inputs, two analog line-level mono inputs,

two stereo outputs, and one mono output channel.

The STAC9752A/9753A includes digital input/output capa-

bility for support of modern PC systems, with an output that

supports the SPDIF format. The STAC9752A/9753A is a

standard 2-channel stereo CODEC. With IDT’s headphone

drive capability, headphones can be driven with without an

external amplifier.

The STAC9752A/9753A may be used as a secondary

CODEC, with the STAC9700/21/56/08/84/50/52 as the pri-

mary, in a multiple CODEC configuration conforming to the

AC'97 Rev. 2.3 specification. This configuration can pro-

vide the true six-channel, AC-3 playback required for DVD

applications.

The STAC9752A/9753A communicates via the five-wire

AC-Link to any digital component of AC'97, providing flexi-

bility in the audio system design.

Packaged in an AC'97 compliant 48-pin TQFP, the

STAC9752A/9753A can be placed on a motherboard,

daughter boards, PCI, AMR, CNR, MDC or ACR cards.

The STAC9752A/9753A provides variable sample rate Dig-

ital-to-Analog (DA) and Analog-to-Digital (AD) conversion,

mixing, and analog processing.

Supported audio sample rates include 48KHz, 44.1KHz,

32KHz, 22.05KHz, 16KHz, 11.025KHz, and 8 KHz; addi-

tional rates are supported in the STAC9752A/9753A soft

audio drivers. All ADCs and DACs operate at 20-bit resolu-

KEY SPECIFICATIONS

•

Analog LINE_OUT SNR: 94dB

Digital DAC SNR: 92dB

Digital ADC SNR: 85dB

Full-scale Total Harmonic Distortion: 0.002%

Crosstalk Between Input Channels: -70dB

Spurious Tone Rejection: 100dB

Stereo Microphone Input

RELATED MATERIALS

•

Data Sheet

IDT™

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A

V 1.5 1206

STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

TABLE OF CONTENTS

1. PRODUCT BRIEF ...................................................................................................................... 6

1.1. Features ............................................................................................................................................ 6

1.2. Description ........................................................................................................................................ 6

1.3. STAC9752A/9753A Block Diagram ................................................................................................... 8

1.4. Key Specifications ............................................................................................................................. 9

1.5. Related Materials .............................................................................................................................. 9

1.6. Additional Support ............................................................................................................................. 9

2. CHARACTERISTICS AND SPECIFICATIONS .......................................................................10

2.1. Electrical Specifications ................................................................................................................... 10

2.2. AC Timing Characteristics ............................................................................................................... 16

3. TYPICAL CONNECTION AND POWER DIAGRAMS .............................................................21

3.1. STAC9752A/9753A Typical Connection Diagram for 48-pin LQFP ................................................ 21

3.2. STAC9752A/9753A Typical Connection Diagram for 32-pad QFN ................................................. 22

3.3. Split Independent Power Supply Operation .................................................................................... 23

3.4. Split Independent Power Supply Operation for the 32-pad QFP Package ......................................24

4. CONTROLLER, CODEC, AND AC-LINK ................................................................................25

4.1. AC-Link Physical interface ............................................................................................................... 25

4.2. Controller to Single CODEC ............................................................................................................ 25

4.3. Controller to Multiple CODECs ........................................................................................................ 26

4.4. Clocking for Multiple CODEC Implementations ............................................................................... 27

4.5. STAC9752A/9753A as a Primary CODEC ...................................................................................... 28

4.6. AC-Link Power Management ........................................................................................................... 28

5. AC-LINK DIGITAL INTERFACE ..............................................................................................31

5.1. Overview ......................................................................................................................................... 31

5.2. AC-Link Serial Interface Protocol .................................................................................................... 32

5.3. AC-Link Output Frame (SDATA_OUT) ............................................................................................ 35

5.4. AC-Link Input Frame (SDATA_IN) .................................................................................................. 38

5.5. AC-Link Interoperability Requirements and Recommendations ...................................................... 42

5.6. Slot Assignments for Audio ............................................................................................................. 43

6. STAC9752A/9753A FUNCTIONAL BLOCKS .........................................................................46

6.1. STAC9752A/9753A Mixer Description ............................................................................................ 46

6.2. SPDIF Digital Mux ...........................................................................................................................48

6.3. PC Beep Implementation ................................................................................................................ 48

7. PROGRAMMING REGISTERS ................................................................................................50

7.1. Register Descriptions ...................................................................................................................... 51

7.2. General Purpose Input & Outputs ................................................................................................... 68

7.3. Extended CODEC Registers Page Structure Definition .................................................................. 72

7.4. STAC9752A/9753A Paging Registers ............................................................................................. 72

7.5. Vendor ID1 and ID2 (Index 7Ch and 7Eh) ...................................................................................... 84

8. LOW POWER MODES ............................................................................................................85

9. MULTIPLE CODEC SUPPORT ...............................................................................................87

9.1. Primary/Secondary CODEC Selection ............................................................................................ 87

9.2. Secondary CODEC Register Access Definitions ............................................................................. 88

10. TESTABILITY ........................................................................................................................89

10.1. ATE Test Mode ............................................................................................................................. 89

11. STAC9752A/9753A PIN DESCRIPTION ...............................................................................90

11.1. Pin Description for the 48-pin LQFP Package ............................................................................... 90

11.2. Pinout List 48-pin LQFP Package ................................................................................................ 91

11.3. Pin Description for the 32-pad QFN Package ............................................................................... 92

11.4. Pinout List 32-pad QFN Package ................................................................................................. 93

11.5. STAC9752A/9753A Digital I/O ...................................................................................................... 93

11.6. STAC9752A/9753A Analog I/O ..................................................................................................... 94

IDT™

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A

V 1.5 1206

STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

11.7. STAC9752A/9753A Filter/References ........................................................................................... 95

11.8. STAC9752A/9753A Power and Ground Signals ........................................................................... 96

11.9. STAC9752A/9753A No Connects ................................................................................................. 96

12. ORDERING INFORMATION ..................................................................................................97

13. PACKAGE DRAWINGS AND PC BOARD LAYOUT INFORMATION .................................98

13.1. 48-Pin LQFP .................................................................................................................................. 98

13.2. 32-Pad QFN .................................................................................................................................. 99

13.3. PC Board Recommendations for 32-pad QFN Package ............................................................. 100

14. SOLDER REFLOW PROFILE ............................................................................................. 101

14.1. Standard Reflow Profile Data ...................................................................................................... 101

14.2. Pb Free Process - Package Classification Reflow Temperatures .............................................. 102

15. APPENDIX A: PROGRAMMING REGISTERS ................................................................... 103

16. REVISION HISTORY ........................................................................................................... 105

IDT™

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A

V 1.5 1206

STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

LIST OF FIGURES

Figure 1. STAC9752A/9753A Block Diagram ................................................................................................. 8

Figure 2. Cold Reset Timing .......................................................................................................................... 16

Figure 3. Warm Reset Timing ........................................................................................................................16

Figure 4. Clocks Timing ................................................................................................................................. 17

Figure 5. Data Setup and Hold Timing ........................................................................................................ 18

Figure 6. Signal Rise and Fall Times Timing ............................................................................................... 19

Figure 7. AC-Link Low Power Mode Timing .................................................................................................. 19

Figure 8. ATE Test Mode Timing ................................................................................................................... 20

Figure 9. STAC9752A/9753A Typical Connection Diagram 48-pin LQFP .................................................... 21

Figure 10. STAC9752A/9753A Typical Connection Diagram 32-pad QFN ................................................. 22

Figure 11. Split Connection Diagram 32-pad QFN ....................................................................................... 24

Figure 12. AC-Link to its Companion Controller ........................................................................................... 25

Figure 13. STAC9752A/9753A Powerdown Timing ...................................................................................... 29

Figure 14. Bi-directional AC-Link Frame with Slot assignments ................................................................... 31

Figure 15. AC-Link Audio Output Frame ...................................................................................................... 35

Figure 16. Start of an Audio Output Frame ................................................................................................... 35

Figure 17. STAC9752A/9753A Audio Input Frame ....................................................................................... 38

Figure 18. Start of an Audio Input Frame ..................................................................................................... 39

Figure 19. Bi-directional AC-Link Frame with Slot assignments ....................................................................43

Figure 20. AC-Link Input Slots Dedicated To CODEC .................................................................................. 44

Figure 21. STAC9752A/9753A 2-Channel Mixer Functional Diagram .......................................................... 47

Figure 22. Example of STAC9752A/9753A Powerdown/Powerup Flow ....................................................... 85

Figure 23. Powerdown/Powerup Flow With Analog Still Alive ..................................................................... 86

Figure 24. Pin Description Drawing .............................................................................................................. 90

Figure 25. STAC9752A/9753A 32 pad QFN Pin Description Drawing ......................................................... 92

Figure 26. Package Drawing - 48-pin LQFP .................................................................................................. 98

Figure 27. Package Drawing - 32-pad QFN .................................................................................................. 99

Figure 28. Recommended PCB Layout for 32-pad QFN Package .............................................................. 100

Figure 29. Reflow Profile ............................................................................................................................ 101

IDT™

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A

V 1.5 1206

STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

LIST OF TABLES

Table 1. Clock mode configuration ................................................................................................................ 17

Table 2. Common Clocks and Sources ......................................................................................................... 18

Table 3. Recommended CODEC ID strapping .............................................................................................. 27

Table 4. AC-Link Output Slots (transmitted from the Controller) ................................................................... 31

Table 5. The AC-Link Input Slots (transmitted from the CODEC) .................................................................32

Table 6. VRA Behavior .................................................................................................................................. 33

Table 7. Output Slot 0 Bit Definitions ............................................................................................................. 36

Table 8. Command Address Port Bit Assignments ........................................................................................ 37

Table 9. Status Address Port Bit Assignments .............................................................................................. 40

Table 10. Status Data Port Bit Assignments .................................................................................................. 41

Table 11. Primary CODEC Addressing: Slot 0 Tag Bits ................................................................................ 42

Table 12. Secondary CODEC Addressing: Slot 0 tag bits ............................................................................. 43

Table 13. AC-Link Output Slots Dedicated To CODEC ................................................................................. 43

Table 14. AC-Link Output Slots Dedicated To Audio ..................................................................................... 44

Table 15. AC-Link Input Slots Dedicated To Audio ....................................................................................... 44

Table 16. Audio Interrupt Slot Definitions ...................................................................................................... 45

Table 17. Digital PC Beep Examples ............................................................................................................. 49

Table 18. Programming Registers ................................................................................................................. 50

Table 19. Extended Audio ID Register Functions .......................................................................................... 64

Table 20. AMAP compliant ............................................................................................................................ 66

Table 21. Hardware Supported Sample Rates .............................................................................................. 67

Table 22. Supported Jack and Mic Sense Functions .................................................................................... 75

Table 23. Reg 68h Default Values ................................................................................................................. 77

Table 24. Gain or Attenuation Examples ....................................................................................................... 77

Table 25. Register 68h/Page 01h Bit Overview ............................................................................................. 77

Table 26. Sensed Bits (Outputs) ................................................................................................................... 79

Table 27. Sensed Bits (Inputs) ...................................................................................................................... 79

Table 28. Low Power Modes ......................................................................................................................... 85

Table 29. CODEC ID Selection .....................................................................................................................87

Table 30. Secondary CODEC Register Access Slot 0 Bit Definitions ...........................................................88

Table 31. Test Mode Activation .....................................................................................................................89

Table 32. ATE Test Mode Operation ............................................................................................................. 89

Table 33. STAC9752A/9753A 48 Pin LQFP Pin List ..................................................................................... 91

Table 34. STAC9752A/9753A 32 Pad QFN Pin List ...................................................................................... 93

Table 35. STAC9752A/9753A Digital Connection Signals ............................................................................ 93

Table 36. STAC9752A/9753A Analog Connection Signals ........................................................................... 94

Table 37. STAC9752A/9753A Filtering and Voltage References .................................................................. 95

Table 38. STAC9752A/9753A Power and Ground Signals ........................................................................... 96

Table 39. STAC9752A/9753A No Connects .................................................................................................. 96

IDT™

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

STAC9752A/9753A

V 1.5 1206

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