TC74LVQ174FEL datasheet, PDF - EEWORLD Datasheet

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TC74LVQ174FEL: DescriptionIC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.300 INCH, EIAJ TYPE2, PLASTIC, SOP-16, FF/Latch; Categorylogic logic; File Size89KB，5 Pages; ManufacturerToshiba Semiconductor; Websitehttp://toshiba-semicon-storage.com/

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TC74LVQ174FEL Overview

IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.300 INCH, EIAJ TYPE2, PLASTIC, SOP-16, FF/Latch

TC74LVQ174FEL Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Toshiba Semiconductor
Parts packaging code	SOIC
package instruction	SOP,
Contacts	16
Reach Compliance Code	unknown
series	LVQ
JESD-30 code	R-PDSO-G16
JESD-609 code	e0
length	10.3 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
Number of digits	6
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	240
propagation delay (tpd)	13 ns
Certification status	Not Qualified
Maximum seat height	1.9 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	5.3 mm
minfmax	70 MHz

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	TC74LVQ174FEL	TC74LVQ174FSEL	TC74LVQ174FSELP	TC74LVQ174FNELP	TC74LVQ174FNEL	TC74LVQ174FELP	TC74LVQ174F
Description	IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.300 INCH, EIAJ TYPE2, PLASTIC, SOP-16, FF/Latch	IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.225 INCH, EIAJ TYPE1, PLASTIC, SSOP-16, FF/Latch	IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.225 INCH, EIAJ TYPE1, PLASTIC, SSOP-16, FF/Latch	IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.150 INCH, PLASTIC, MS-012AC, SOP-16, FF/Latch	IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.150 INCH, PLASTIC, MS-012AC, SOP-16, FF/Latch	IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.300 INCH, EIAJ TYPE2, PLASTIC, SOP-16, FF/Latch	IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.300 INCH, EIAJ TYPE2, PLASTIC, SOP-16, FF/Latch
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Toshiba Semiconductor	Toshiba Semiconductor	Toshiba Semiconductor	Toshiba Semiconductor	Toshiba Semiconductor	Toshiba Semiconductor	Toshiba Semiconductor
Parts packaging code	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC	SOIC
package instruction	SOP,	0.225 INCH, EIAJ TYPE1, PLASTIC, SSOP-16	LSSOP,	SOP,	SOP,	SOP,	SOP, SOP16,.3
Contacts	16	16	16	16	16	16	16
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
Number of functions	1	1	1	1	1	1	6
Number of terminals	16	16	16	16	16	16	16
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	LSSOP	LSSOP	SOP	SOP	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	0.65 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead	-
series	LVQ	LVQ	LVQ	LVQ	LVQ	LVQ	-
JESD-609 code	e0	e0	e0	-	-	e0	e0
length	10.3 mm	5 mm	5 mm	9.9 mm	9.9 mm	10.3 mm	-
Number of digits	6	6	6	6	6	6	-
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	-
Peak Reflow Temperature (Celsius)	240	240	240	240	240	240	-
propagation delay (tpd)	13 ns	13 ns	13 ns	13 ns	13 ns	13 ns	-
Maximum seat height	1.9 mm	1.6 mm	1.6 mm	1.75 mm	1.75 mm	1.9 mm	-
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	-
Minimum supply voltage (Vsup)	2 V	2 V	2 V	2 V	2 V	2 V	-
Terminal surface	TIN LEAD	TIN LEAD	TIN LEAD	-	-	TIN LEAD	Tin/Lead (Sn/Pb)
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
width	5.3 mm	4.4 mm	4.4 mm	3.9 mm	3.9 mm	5.3 mm	-
minfmax	70 MHz	70 MHz	70 MHz	70 MHz	70 MHz	70 MHz	-

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