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TC74LVQ174FNEL

Description
IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.150 INCH, PLASTIC, MS-012AC, SOP-16, FF/Latch
Categorylogic    logic   
File Size89KB,5 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
Download Datasheet Parametric Compare View All

TC74LVQ174FNEL Overview

IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.150 INCH, PLASTIC, MS-012AC, SOP-16, FF/Latch

TC74LVQ174FNEL Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerToshiba Semiconductor
Parts packaging codeSOIC
package instructionSOP,
Contacts16
Reach Compliance Codeunknown
seriesLVQ
JESD-30 codeR-PDSO-G16
length9.9 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeD FLIP-FLOP
Number of digits6
Number of functions1
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)240
propagation delay (tpd)13 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width3.9 mm
minfmax70 MHz

TC74LVQ174FNEL Related Products

TC74LVQ174FNEL TC74LVQ174FSEL TC74LVQ174FSELP TC74LVQ174FNELP TC74LVQ174FELP TC74LVQ174FEL TC74LVQ174F
Description IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.150 INCH, PLASTIC, MS-012AC, SOP-16, FF/Latch IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.225 INCH, EIAJ TYPE1, PLASTIC, SSOP-16, FF/Latch IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.225 INCH, EIAJ TYPE1, PLASTIC, SSOP-16, FF/Latch IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.150 INCH, PLASTIC, MS-012AC, SOP-16, FF/Latch IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.300 INCH, EIAJ TYPE2, PLASTIC, SOP-16, FF/Latch IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.300 INCH, EIAJ TYPE2, PLASTIC, SOP-16, FF/Latch IC LVQ SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, 0.300 INCH, EIAJ TYPE2, PLASTIC, SOP-16, FF/Latch
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible incompatible incompatible
Maker Toshiba Semiconductor Toshiba Semiconductor Toshiba Semiconductor Toshiba Semiconductor Toshiba Semiconductor Toshiba Semiconductor Toshiba Semiconductor
Parts packaging code SOIC SOIC SOIC SOIC SOIC SOIC SOIC
package instruction SOP, 0.225 INCH, EIAJ TYPE1, PLASTIC, SSOP-16 LSSOP, SOP, SOP, SOP, SOP, SOP16,.3
Contacts 16 16 16 16 16 16 16
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown
JESD-30 code R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
Load capacitance (CL) 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF
Logic integrated circuit type D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
Number of functions 1 1 1 1 1 1 6
Number of terminals 16 16 16 16 16 16 16
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP LSSOP LSSOP SOP SOP SOP SOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE, LOW PROFILE, SHRINK PITCH SMALL OUTLINE, LOW PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 1.27 mm 0.65 mm 0.65 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL DUAL
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
Is it lead-free? Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead -
series LVQ LVQ LVQ LVQ LVQ LVQ -
length 9.9 mm 5 mm 5 mm 9.9 mm 10.3 mm 10.3 mm -
Number of digits 6 6 6 6 6 6 -
Output polarity TRUE TRUE TRUE TRUE TRUE TRUE -
Peak Reflow Temperature (Celsius) 240 240 240 240 240 240 -
propagation delay (tpd) 13 ns 13 ns 13 ns 13 ns 13 ns 13 ns -
Maximum seat height 1.75 mm 1.6 mm 1.6 mm 1.75 mm 1.9 mm 1.9 mm -
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V -
Minimum supply voltage (Vsup) 2 V 2 V 2 V 2 V 2 V 2 V -
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED -
width 3.9 mm 4.4 mm 4.4 mm 3.9 mm 5.3 mm 5.3 mm -
minfmax 70 MHz 70 MHz 70 MHz 70 MHz 70 MHz 70 MHz -
JESD-609 code - e0 e0 - e0 e0 e0
Terminal surface - TIN LEAD TIN LEAD - TIN LEAD TIN LEAD Tin/Lead (Sn/Pb)
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