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935279979115

Description
AUP/ULP/V SERIES, DUAL 1-INPUT INVERT GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6
Categorylogic    logic   
File Size194KB,19 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Download Datasheet Parametric View All

935279979115 Overview

AUP/ULP/V SERIES, DUAL 1-INPUT INVERT GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6

935279979115 Parametric

Parameter NameAttribute value
package instructionVSON,
Reach Compliance Codeunknow
seriesAUP/ULP/V
JESD-30 codeR-PDSO-N6
JESD-609 codee3
length1.45 mm
Logic integrated circuit typeINVERTER
Number of functions2
Number of entries1
Number of terminals6
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeVSON
Package shapeRECTANGULAR
Package formSMALL OUTLINE, VERY THIN PROFILE
propagation delay (tpd)20.9 ns
Maximum seat height0.5 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)0.8 V
Nominal supply voltage (Vsup)1.1 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTIN
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationDUAL
width1 mm
Base Number Matches1
74AUP2G04
Low-power dual inverter
Rev. 5 — 5 March 2012
Product data sheet
1. General description
The 74AUP2G04 provides two inverting buffers.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
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