AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
Hermetic, Multi-Chip Module
(MCM)
64Mb, 2M x 32, 3.3Volt Boot Block FLASH
Array
Available via Applicable Specifications:
•
MIL-PRF-38534, Class H
I/O0
DQ0
I/O1
DQ1
DQ2
I/02
I/O3
DQ3
I/O4
DQ4
I/O5
DQ5
I/O6
DQ6
DQ7
I/O7
GND
DQ8
I/O8
DQ9
I/O9
DQ10
I/O10
DQ11
I/O11
DQ12
I/012
DQ13
I/O13
DQ14
I/O14
DQ15
I/O15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
AS8FLC2M32
FLASH
FIGURE 1: PIN ASSIGNMENT
(Top View)
RESET\
A0
A1
A2
A3
A4
A5
CS3\
GND
CS4\
WE1\
A6
A7
A8
A9
A10
VCC
09
08
07
06
05
04
03
02
01
68
67
66
65
64
63
62
61
60
59
78
57
76
55
54
53
52
51
50
49
I/O16
DQ16
I/O17
DQ17
I/O18
DQ18
I/O19
DQ19
I/O20
DQ20
I/O21
DQ21
I/O22
DQ22
DQ23
I/O23
GND
I/O24
DQ24
I/O25
DQ25
I/O26
DQ26
I/O27
DQ27
I/O28
DQ28
DQ29
I/O29
DQ30
I/O30
DQ31
I/O31
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
64Mb device, total density, organized as 2M x 32
Bottom Boot Block (Sector) Architecture
(Contact factory for top boot)
Operation with single 3.0V Supply
Available in multiple Access time variations
Individual byte control via individual byte selects (CSx\)
Low Power CMOS
1,000,000 Erase/Program Cycles
Minimum 1,000,000 Program/Erase Cycles per sector
guaranteed
Sector Architecture:
•
One 16K byte, two 8K byte, one 32K byte and
thirty-one 64Kbyte sectors (byte mode)
Any combination of sectors can be concurrently erased
MCM supports full array (multi-chip) Erase
Embedded Erase and Program Algorithms
Erase Suspend/Resume; Supports reading data from or
programming data to a sector not being Erased
TTL Compatible Inputs and Outputs
Military and Industrial operating temperature ranges
[Package Designator QT]
48
47
46
45
44
39
40
41
42
DQ8
I/O8
DQ9
I/O9
DQ10
I/O10
VCC
A11
A12
A13
A14
A15
A16
CS1\
OE\
CS2\
A17
WE2\
WE3\
WE4\
A18
A19
NC
A20
Pin Assignment
(Top View)
Reset\
CS2\
GND
DQ11
I/O11
I/O15
DQ15
DQ14
I/O14
I/O24
DQ24
I/O25
DQ25
I/O26
DQ26
A7
A12
VCC
CS4\
NC
DQ27
I/O27
43
I/O31
DQ31
DQ30
I/O30
DQ29
I/O29
DQ28
I/O28
I/O13
DQ13
DQ12
I/O12
A14
A16
A11
A0
A18
DQ0
I/O0
DQ1
I/O1
DQ2
I/O2
A10
A9
A15
VCC
CS1\
A19
I/O3
DQ3
OE\
A17
WE\
I/O7
DQ7
DQ6
I/O6
A4
A5
A6
NC
CS3\
GND
DQ19
I/O19
A1
A2
A3
I/O23
DQ23
DQ22
I/O22
66 HIP
A20
NC
A13
A8
I/O16
DQ16
I/O17
DQ17
I/O18
DQ18
OPTION
Access Speed
70ns
90ns
100ns
120ns
Package
Ceramic Quad Flat Pack
Ceramic Hex Inline Pack
MARKING
-70
-90
-100
-120
I/O5
DQ5
I/O4
DQ4
I/O21
DQ21
DQ20
I/O20
[Package Designator
P
H]
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8FLC2M32B is a 64Mb
FLASH Multi-Chip Module organized as 2M x 32 bits. The
module achieves high speed access, low power consumption
and high reliability by employing advanced CMOS memory
technology. The military grade product is manufactured in
compliance to the MIL-PRF-38534 specifications, making the
AS8FLC2M32B ideally suited for military or space applications.
The module is offered in a 68-lead 0.990 inch square ceramic
quad flat pack or 66-lead 1.185inch square ceramic Hex In-line
Package (HIP). The CQFP package design is targeted for those
applications, which require low profile SMT Packaging.
Q
P
Temperature Range
Full Mil (MIL-PRF-38534, Class H) /Q
Military Temp (-55
o
C to +125
o
C)
/XT
o
o
Industrial (-40 C to +85 C) /IT
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS8FLC2M32B
Rev. 1.1 5/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
BLOCK DIAGRAM
68-Ld. CQFP, Package "QT"
WE1\ CS1\
RESET\
OE\
A0-Ax
WE2\ CS2\
WE3\ CS3\
WE4\ CS4\
AS8FLC2M32
FLASH
before executing the erase operation. During erasure, the
device automatically times the erase pulse widths and verifies
proper cell margin.
The host system can detect whether a program or erase
operation is complete by observing the RY/BY\ pin, or by
reading the DQ7 (Data\ Polling) and DQ6 (toggle) STATUS
BITS. After a program or erase cycle has been completed, the
device is ready to read array data or accept another command.
The SECTOR ERASE ARCHITECTURE allows memory
sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased
when shipped from ASI.
Hardware data protection measures include a low VCC
detector that automatically inhibits WRITE operations during
power transitions. The hardware sector protection features
disables both program and erase operation in any combination
of the sectors of memory. This can be achieved in-system or
via specially adapted commercial programming equipment.
The ERASE SUSPEND feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any sector which is not selected for erasure. True
BACKGROUND ERASE can thus be achieved.
The HARDWARE RESET\ PIN terminates any operation in
progress and resets the internal state machine to a READ
operation. The RESET\ pin may be tied to the system reset
circuitry.
1M
2
x8
1M
2
x8
1M
2
x8
1M
2
x8
DQ
I/O0-7
DQ
I/O8-15
DQ
I/O16-23
DQ
I/O24-31
BLOCK DIAGRAM
P
66-Ld. HIP, Package "H"
CS1\
WE\
RESET\
OE\
A0-Ax
CS2\
CS3\
CS4\
2
x8
1M
2
x8
1M
2
x8
1M
2
x8
1M
DQ
I/O0-7
DQ
I/O8-15
DQ
DQ
I/O16-23
DQ
I/O24-31
The device requires only a single 3.3volt power supply for
both READ and WRITE operations. Internally generated and
regulated voltages are provided for the program and erase
functions.
The device is entirely command set compatible with the
JEDEC SINGLE POWER FASH STANDARD. Commands are
written to the command register using standard
microprocessor write timings. Register contents serve as
input to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch
addresses and data required for the programming or erase
function(s). Reading data out of the array is similar to reading
from other electrically programmable devices.
Device programming occurs by executing the program command
sequence. This initiates the EMBEDDED PROGRAM algorithm
that automatically times the WRITE PULSE widths and cycle
and verifies each cell for proper cell margins. The UNLOCK
BYPASS mode facilitates faster programming times by requiring
only two WRITE cycles to program data instead of four.
Device erasure occurs by executing the erase command
sequence. This initiates the Embedded Erase algorithm, an
internal algorithm that automatically pre-programs the array
AS8FLC2M32B
Rev. 1.1 5/08
LOGIC DIAGRAM (Byte)
VCC
GND
DQ (byte)
RY/BY\
RESET\
State
Control
Command
Register
Erase Voltage
Generator
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Sector
Switches
Address Latch
Y-Decoder
I/O Buffers
WEx\
Data Latch
CSx\
OE\
Y-Gating
VCC Detector
Timer
X-Decoder
Cell Matrix
A0-Ax
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
A system reset would then also reset the FLASH device,
enabling the system microprocessor to read the boot-up
firmware from the FLASH memory array. The device offers two
power-saving features. When addresses have been stable for
a specified amount of time, the device enters the AUTOMATIC
SLEEP MODE. The system can also place the device into the
STANDBY mode. Power consumption is greatly reduced in
both these modes.
AS8FLC2M32
FLASH
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that
assert valid data on the device address inputs produce valid
data on the data outputs. The device remains enabled for read
access until the command register contents are altered.
See READING ARRAY DATA for more information. Refer to
AC Read Operations table data for timing specifications
relevant to this operational mode.
Device Bus Operations
This section describes the use of the command register for
setting and controlling the bus operations. The command
register itself does not occupy any addressable memory
locations. The register is composed of a series of latches that
store the commands, addresses and data information needed
to execute the indicated command. The contents of the register
serve as the input to the internal state machine. The state
machine output dictates the function of the device. Table 1
lists the device bus operations, the inputs and control/stimulus
levels they require, and the resulting output. The following
subsections describe each of these operations in further detail.
Writing Commands/Command Sequences
To WRITE a command or command sequence, the system must
drive CSx\, WEx\ to VIL and OE\ to VIH.
An ERASE command operation can erase one sector, multiple
sectors, or the entire array. Table 2 indicates the address space
contained within each sector within the array. A sector address
consists of the address bits required to uniquely select a sector.
The “Command Definitions” section has details on erasure of
a single, multiple sectors, the entire array or suspending/
resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on each of the Data input/
output bits within each byte of the MCM FLASH array.
Standard read cycle timings apply in this mode. Refer to the
Autoselect Mode and Autoselect Command Sequence sections
for more information.
ICC2 in the DC Characteristics table represents that active
current specification for the WRITE mode. The AC
Characteristics section contains timing specifications for Write
Operations.
OPERATION
ADDRESSES
DATA BUS (DQ0-DQX)
D0-D7 Out
D8-D15 Out
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the
CSx\ and OE\ pins to VIL. Chip Select CSx\ is the power and
chip select control of the byte or bytes targeted by the system
(user). Output Enable [OE\] is the output control and gates
array data to the output pins. Write (byte) Enables [WEx\]
should remain at VIH levels.
The internal state machine is set for reading array data upon
device power-up, or after a HARDWARE RESET. This ensures
that no spurious alteration of the memory content occurs during
Table 1
RESET\
CS1\
L
H
H
H
H
L
L
H
H
H
H
L
VCC +/- 0.3V
X
L
VID
VID
VID
Legend
Notes
VCC +/- 0.3V
L
X
L
L
CS2\
H
L
H
H
L
H
L
H
H
L
VCC +/- 0.3V
L
X
L
L
CS3\
H
H
L
H
L
H
H
L
H
L
VCC +/- 0.3V
L
X
L
L
CS4\
H
H
H
L
L
H
H
H
L
L
VCC +/- 0.3V
L
X
L
L
L
H
H
H
L
X
H
X
L
L
H
L
H
H
L
X
H
X
L
L
H
H
L
H
L
X
H
X
L
L
H
H
H
WE1\ WE2\ WE3\ WE4\ OE\
H
L
READ
A0-Ax In
D16-D31 Out
D24-D31 Out
D0-D31 Out
H
H
H
L
L
X
H
X
L
L
X
H
X
H
H
Standby
Output Diable
Reset
Sector Protect
Sector Unprotect
X
X
X
SECTOR ADDRESS
A7=L, A2=H, A1=L
SECTOR ADDRESS
A7=L, A2=H, A1=L
A
IN
H
WRITE
A0-Ax In
D0-D7 In
D8-D15 In
D16-D31 In
D24-D31 In
D0-D31 In
D
IN
, D
OUT
D
IN
, D
OUT
D
IN
X
X
X
X
X
X
X
X
X
Temporary Sector Unprotect
L=Logic=VIL, H=Logic High=VIH, VID=12.0 +/-0.5V, X= Don't Care, A
IN
=Address In, D
OUT
=Data Out
AS8FLC2M32B
Rev. 1.1 5/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
Program and Erase Operation Status
During an ERASE or PROGRAM operation, the system may
check the status of the operation by reading the status bits on
each of the seven data I/O bits within each byte of the MCM
FLASH array. Standard READ cycle timings and ICC read
specifications apply. Refer to “Write Operation Status” for
more information, and to “AC Characteristics” for timing
specifications.
AS8FLC2M32
FLASH
The AUTOMATIC SLEEP mode is independent of the CSx\,
WEx\ and OE\ control signals. Standard address access timings
provide new data when addresses are changed. While in sleep
mode, output data is latched and always available to the system.
ICC5 in the “DC Characteristics Table represents the
AUTOMATIC SLEEP mode current usage.
RESET\: Hardware Reset Pin
Standby Mode
When the system is not READING or WRITING to the device,
it can place the device in the standby mode to save on power
consumption.
The RESET\ pin provides a hardware method of resetting the
device to reading array data. When the RESET\ pin is driven
low for at least a period of tRP, the device immediately terminates
any operation in progress, tristates all output pins, and ignores
all READ/WRITE commands for the duration of the RESET\
pulse. The device also resets the internal state machine to
reading array data. The operation that was interrupted should
be reinitiated once the device is ready to accept another
command sequence, to ensure data integrity.
The device enters the CMOS STANDBY mode when the CSx\
and RESET\ pins are held at VCC+/-0.3v. If CSx\ and RESET\
are held at VIH, but not within VCC+/-0.3v, the device will be in
STANDBY mode but at levels higher than achievable in full
CMOS STANDBY. The device requires standard access time
(tCE) for read access when the device is in either of these Current is reduced for the duration of the RESET\ pulse. When
RESET\ is held at VSS+/-0.3v, the device draws CMOS
STANDBY modes, before it is ready to READ data.
STANDBY current (ICC4). If RESET\ is held at VIL but not
If the device is deselected during ERASURE or within the limits of VCC +/- 0.3v, the MCM Array will be in
PROGRAMMING, the device draws active current until the STANDBY, but current limits will be higher than those listed
under ICC4.
operation is completed.
In the DC Characteristics table, ICC3 and ICC4 represent the
The RESET\ pin may be tied to the system reset circuitry. A
system reset would thus also reset the FLASH array, enabling
STANDBY MODE currents.
the system to read the boot-up firmware code from the boot
block area of the memory.
Automatic Sleep Mode
The AUTOMATIC SLEEP mode minimizes FLASH device
energy consumption. The device automatically enables this
mode when addresses remain stable for tACC + 30ns.
AS8FLC2M32B
Rev. 1.1 5/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
AUSTIN SEMICONDUCTOR, INC.
Austin Semiconductor, Inc.
If RESET\ is asserted during a PROGRAM or ERASE opera-
tion, the RY/BY\ pin remains a “0” (busy) until the internal
reset operation is complete, which requires a time of tREADY.
The system can thus monitor RY/BY\ to determine whether the
RESET operation is complete. If RESET\ is asserted when a
AS8FLC2M32
FLASH
Autoselect Code Table
PROGRAM or ERASE operation is not executing (RY/BY\ pin
is “1”), the RESET operation is completed within a time of
tREADY. The system can read data tRH after the RESET\ pin
returns to VIH.
Refer to the “AC Characteristics” tables for RESET\ parameters.
identification, and sector protection verification through
identifier codes output via the appropriate Byte DQ’s. This
mode is primarily intended for programming equipment to
automatically match a device to be programmed with its
corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the
command register.
When using programming equipment (modified to support
multi-byte devices, or supplied from the programming
equipment provider as such), the autoselect mode requires
VID (11.5v to 12.5v) on address pin A9. Address pins A6, A1,
and A0 must be as shown in the Autoselect Table below. In
addtion, when verifying sector protection, the sector address
must appear on the appropriate highest order address bits.
When all necessary bits have been set as required, the
programming equipment may then read the corresponding
identifier code on the appropriate Byte DQ’s.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command register.
Output Disable Mode
When the OE\ input is at VIH, output from the device is disabled.
The output pins are placed in the high Impedance State.
Autoselect Mode
The autoselect mode provides manufacturer and device
AS8FLC2M32B
Rev. 1.1 5/08
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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