AT25020N-10SJ-2.7 datasheet, PDF

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AT25020N-10SJ-2.7: DescriptionEEPROM, 256X8, Serial, PDSO8; Categorystorage storage; File Size200KB，19 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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AT25020N-10SJ-2.7 Overview

EEPROM, 256X8, Serial, PDSO8

AT25020N-10SJ-2.7 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microchip
package instruction	0.150 INCH, PLASTIC, SOIC-8
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum clock frequency (fCLK)	2.1 MHz
Data retention time - minimum	100
Durability	1000000 Write/Erase Cycles
JESD-30 code	R-PDSO-G8
JESD-609 code	e3
length	4.9 mm
memory density	2048 bit
Memory IC Type	EEPROM
memory width	8
Humidity sensitivity level	1
Number of functions	1
Number of terminals	8
word count	256 words
character code	256
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256X8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	260
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	1.75 mm
Serial bus type	SPI
Maximum standby current	0.000005 A
Maximum slew rate	0.006 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	3.9 mm
Maximum write cycle time (tWC)	10 ms
write protect	HARDWARE/SOFTWARE

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Features

•

Serial Peripheral Interface (SPI) Compatible

•

Supports SPI Modes 0 (0,0) and 3 (1,1)

•

Low-voltage and Standard-voltage Operation

– 2.7 (V

= 2.7V to 5.5V)

•

3.0 MHz Clock Rate (5V)

•

8-byte Page Mode

•

Block Write Protection

•

– Protect 1/4, 1/2, or Entire Array

Write Protect (WP) Pin and Write Disable Instructions for

Both Hardware and Software Data Protection

Self-timed Write Cycle (10 ms max)

High Reliability

– Endurance: One Million Write Cycles

– Data Retention: 100 Years

Automotive Grade, Extended Temperature and Lead-Free Devices Available

8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TAP Packages

SPI Serial

EEPROMs

1K (128 x 8)

2K (256 x 8)

4K (512 x 8)

Description

The AT25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable

programmable read only memory (EEPROM) organized as 128/256/512 words of 8

bits each. The device is optimized for use in many industrial and commercial applica-

tions where low-power and low voltage operation are essential. The AT25010/020/040

is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead

TAP packages.

The AT25010/020/040 is enabled through the Chip Select pin (CS) and accessed via a

3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and

Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-

rate ERASE cycle is required before WRITE.

BLOCK WRITE protection is enabled by programming the status register with one of

four blocks of write protection. Separate program enable and program disable instruc-

tions are provided for additional data protection. Hardware data protection is provided

via the WP pin to protect against inadvertent write attempts. The HOLD pin may be

used to suspend any serial communication without resetting the serial sequence.

AT25010

AT25020

AT25040

Pin Configurations

Pin Name

SCK

GND

VCC

HOLD

Function

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

Power Supply

Write Protect

Suspends Serial Input

GND

8-lead PDIP

VCC

HOLD

SCK

8-lead SOIC

VCC

HOLD

SCK

8-lead MAP/TAP

VCC

HOLD

SCK

GND

Bottom View

Rev. 0606K–SEEPR–01/03

AT25010/020/040

Serial Interface

Description

MASTER:

The device that generates the serial clock.

SLAVE:

Because the Serial Clock pin (SCK) is always an input, the AT25010/020/040

always operates as a slave.

TRANSMITTER/RECEIVER:

The AT25010/020/040 has separate pins designated for

data transmission (SO) and reception (SI).

MSB:

The Most Significant Bit (MSB) is the first bit transmitted and received.

SERIAL OP-CODE:

After the device is selected with CS going low, the first byte will be

received. This byte contains the op-code that defines the operations to be performed.

The op-code also contains address bit A8 in both the READ and WRITE instructions.

INVALID OP-CODE:

If an invalid op-code is received, no data will be shifted into the

AT25010/020/040, and the serial output pin (SO) will remain in a high impedance state

un til the falling edge of CS is de tected a gain. This will reinitialize the serial

communication.

CHIP SELECT:

The AT25010/020/040 is selected when the CS pin is low. When the

device is not selected, data will not be accepted via the SI pin, and the serial output pin

(SO) will remain in a high impedance state.

H O LD :

Th e H OLD p in is u se d in co n jun ctio n w it h the C S pin to s e le ct th e

AT25010/020/040. When the device is selected and a serial sequence is underway,

HOLD can be used to pause the serial communication with the master device without

resetting the serial sequence. To pause, the HOLD pin must be brought low while the

SCK pin is low. To resume serial communication, the HOLD pin is brought high while the

SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored

while the SO pin is in the high impedance state.

WRITE PROTECT:

The write protect pin (WP) will allow normal read/write operations

when held high. When the WP pin is brought low, all write operations are inhibited.

WP going low while CS is still low will interrupt a write to the AT25010/020/040. If the

internal write cycle has already been initiated, WP going low will have no effect on any

write operation.

0606K–SEEPR–01/03

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