That is, the larger the frequency f, the smaller the impedance Z of the capacitor. When the frequency is low, the impedance Z of capacitor C is relatively large, so the useful signal can pass smoothly; When the frequency is high, the impedance Z of capacitor C is already very small, which is equivalent to short-circuiting the high-frequency noise to GND. 2. When will capacitor filtering fail? Capacitors are often used for filtering in rectification, and there is often a saying that "large capacitors filter low frequencies, small capacitors filter high frequencies". Take the common surface-mount MLCC ceramic capacitor as an example, the equivalent model is as follows:
Since the equivalent model contains both capacitor C and inductor L, forming a second-order system, there is instability. For the circuit loop, resonance will occur, and the resonance point is at the following frequency:
That is, it is often said that it is a capacitor before the resonance point, and it is no longer a capacitor after the resonance point. 3. When to use LC filtering If the inductor L is connected in series and then connected in parallel to form C, an LC filter is formed:
A single capacitor C is a first-order system, and a single inductor L is also a first-order system, with an amplitude attenuation slope of -20dB. But for the second-order system composed of LC, the amplitude attenuation slope is -40dB, which is closer to the ideal "steep" cut-off frequency effect, that is, the filtering effect is better.
Fourth, what is the PWM frequency? When mentioning PWM, for example, we will say that 20kHz PWM is used to drive the motor. But in fact, this 20kHz only means that the pulse period of PWM is 50us:
For step signals, since the rise time tr is infinitesimal, the frequency f is infinite. When the frequency is high, the parasitic parameters cannot be ignored, which will cause many resonance problems. From the signal point of view, a very steep step signal will have overshoot and oscillation problems. Simply put, the larger the frequency f, the wider the frequency occupied by the noise, that is, the worse the EMC characteristics will be. 5. How to match the schematic diagram with the PCB Due to the problem of subdividing the types of work, the schematic diagram and the PCB are separated, and two groups of people perform the work separately:
Its implicit problem is that on the PCB, there is actually a line between the negative pole of V1 and the negative pole of C1 (the word used in the PCB layout tool software is more accurate, Trace). A->B->C is often concerned in the design stage. If there is an EMC problem, in addition to finding the circuit parameter problem on the schematic diagram, special attention should be paid to C->D, that is, the return path.
For example, during the EMC test, the signal collected by the ADC of the MCU is interfered with. In addition to analyzing it on the schematic diagram, highlight the signal on the PCB, and then patiently look for any obstructions in the return path of the signal: