CY2XP304BVXC datasheet, PDF - EEWORLD Datasheet

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CY2XP304BVXC: DescriptionClock Generator, 1500MHz, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36; CategoryThe embedded processor and controller Microcontrollers and processors; File Size244KB，12 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

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CY2XP304BVXC Overview

Clock Generator, 1500MHz, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36

CY2XP304BVXC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	VFBGA,
Contacts	36
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	R-PBGA-B36
JESD-609 code	e1
length	8 mm
Humidity sensitivity level	3
Number of terminals	36
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	1500 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	1500 MHz
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.75 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	6 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

CY2XP304BVXC Preview

ADVANCE

INFORMATION

CY2XP304

High-Frequency Programmable PECL

Clock Generation Module

Features

• Jitter peak-peak (TYPICAL) = 65 ps

• Four Low-skew LVPECL outputs

• Phase-locked loop (PLL) multiplier select

• Serially-configurable multiply ratios

• Eight-bit feedback counter and six-bit reference

counter for high accuracy

• HSTL inputs—HSTL-to-LVPECL level translation

• 125- to 400-MHz output range for high-speed applica-

tions (500-MHz option available)

• High-speed PLL bypass mode to 1.5 GHz

• 36-VFBGA, 6 × 8 × 1 mm

• 3.3V operation

Block Diagram

PLL_MULT

CLK0

CLK0B

CLK1

XIN

XOUT

SER CLK

SER DATA

INA

INAB

CLK_SEL

XTAL

OSCILLATOR

PLL

CLK1B

CLK2

CLK2B

CLK3

CLK3B

Pin Configuration

CLK0

CLK0B

CLK2B

CLK3

CLK3B

CLK1

CLK1B

CLK2

VDDA

GND

TOP VIEW

GND

VDDA

GND

SER_D

ATA

VDDB

VDDA

Xout

SER_CL

GND

VDDB

Xin

GND

VDDA

VDDB

GND

PLL_MUL

CLK_SE

INA

INAB

VDDA

Cypress Semiconductor Corporation

Document #: 38-07589 Rev. **

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised November 25, 2003

ADVANCE

INFORMATION

Pin Description

Pin #

A1,B1,G3,G4

A4,B2,C1,C3,C4,F3,F4,G2,G5,B5

A5,H1,H2,H4,H5

F1,G1

Pin Name

VDDB

XIN

XOUT

GND

VDDA

CLK0

CLK0B

CLK1

CLK1B

CLK2

CLK2B

CLK3

CLK3B

Reference Crystal Input

Reference Crystal Feedback

Ground

3.3V Power Supply

LVPECL Clock Output

(Complement)

LVPECL Clock Output

(Complement)

LVPECL Clock Output

(Complement)

LVPECL Clock Output

(Complement)

Pin Description

3.3V Power Supply for Crystal Driver

CY2XP304

SER_CLK

Serial Interface Clock

SER_DATA

Serial Interface Data

PLL_MULT

PLL Multiplier Select Input,

Internal pull-up resistor, see

Frequency Table

CLK_SEL

INA,INAB

Clock Select Input, Internal Pull down.

High select INA/INAB, Internal PLL

is bypassed. Low select internal PLL

Differential Clock Input pair,

used in PLL-bypassed mode

No Connect

Frequency Table

PLL_Mult

M (PLL Multiplier)

x16

Example Input Crystal Frequency

25 MHz

31.25 MHz

15.625 MHz

CLK[0:3],CLKB[0:3]

400 MHz

500 MHz

125 MHz

Data is allowed to change only at LOW period of clock, and

must be stable at the HIGH period of clock. To acknowledge,

drive the S

data

LOW before the S

clk

rising edge and hold it

LOW until the S

clk

falling edge.

Serial Interface Format

Each slave carries an address. The data transfer is initiated by

a start signal (S). Each transfer segment is one byte in length.

The slave address and the read/write bit are first sent from the

master device after the start signal. The addressed slave

device must acknowledge (Ack) the master device. Depending

on the Read/Write bit, the master device will either write data

into (logic 0) or read data (logic 1) from the slave device. Each

time a byte of data is successfully transferred, the receiving

device must acknowledge. At the end of the transfer, the

master device will generate a stop signal (P).

Serial Interface Transfer Format

Figure 2

shows the serial interface transfer format used with

the CY2XP304. Two dummy bytes must be transferred before

the first data byte. The CY2XP304 has only three bytes of

latches to store information, and the third byte of data is

reserved. Extra data will be ignored.

Page 2 of 12

CY2XP304 Two-Wire Serial Interface

Introduction

The CY2XP304 has a two-wire serial interface designed for

data transfer operations, and is used for programming the P

and Q values for frequency generation. S

clk

is the serial clock

line controlled by the master device. S

data

is a serial bidirec-

tional data line. The CY2XP304 is a slave device and can

either read or write information on the dataline upon request

from the master device.

Figure 1

shows the basic bus connections between master

and slave device. The buses are shared by a number of

devices and are pulled high by a pull-up resistor.

Serial Interface Specifications

Figure 2

shows the basic transmission specification. To begin

and end a transmission, the master device generates a start

signal (S) and a stop signal (P). Start (S) is defined as

switching the S

data

from HIGH to LOW while the S

clk

is at

HIGH. Similarly, stop (P) is defined as switching the S

data

from

LOW to HIGH while holding the S

clk

HIGH. Between these two

signals, data on S

data

is synchronous with the clock on the S

clk

Document #: 38-07589 Rev. **

ADVANCE

INFORMATION

CY2XP304

d a ta

clk

c lk

_ C

d ata

_ C

d ata

_ C

clk

_ in

d ata

_ in

clk

_ in

d ata

_ in

M a s te r D e vic e

S lav e D ev ice

Figure 1. Device Connections

clk

data

Start (S)

valid data

Acknowledge

Stop (P)

Figure 2. Serial Interface Specifications

1 bit

7 bits

Slave Address

1 bit

R/W

1 bit

8 bits

Dummy Byte 0

1 bit

8 bits

1 bit

8 bits

1 bit

Ack

Dummy Byte 1

Ack

Data 0

Ack

Data 1

8 bits

Ack

1 bit

Figure 3. CY2XP304 Transfer Format

Serial Interface Address for the CY2XP304

R/W

Serial Interface Programming for the CY2XP304

Data0

Data1

Data2

QCNTBYP

P<7>

Reserved

SELPQ

P<6>

Reserved

Q<5>

P<5>

Reserved

Q<4>

P<4>

Reserved

Q<3>

P<3>

Reserved

Q<2>

P<2>

Reserved

Q<1>

P<1>

Reserved

Q<0>

P<0>

Reserved

To program the CY2XP304 using the two-wire serial interface,

set the SELPQ bit HIGH. The default setting of this bit is LOW.

The P and Q values are determined by the following formulas:

final

= (P

7..0

+ 3) * 2

final

= Q

5..0

+ 2.

If the QCNTBYP bit is set HIGH, then Q

final

defaults to a value

of 1. The default setting of this bit is LOW.

If the SELPQ bit is set LOW, the PLL multipliers will be set

using the values in the Select Function Table.

CyberClocks™ has been developed to generate P and Q

values for stable PLL operation. This software is downloadable

from www.cypress.com.

Document #: 38-07589 Rev. **

Page 3 of 12

ADVANCE

INFORMATION

PLL Frequency = Reference x P/Q = Output

Reference

VCO

Output

CY2XP304

PLL

Figure 4. PLL Block Diagram

Functional Specifications

Crystal Input

The CY2XP304 receives its reference from an external crystal.

Pin XIN is the reference crystal input, and pin XOUT is the

reference crystal feedback. The parameters for the crystal are

given on page 5 of this data sheet. The oscillator circuit

requires external capacitors. Please refer to the application

note entitled

Crystal Oscillator Topics

for details.

Select Input

There are two select input pins, the PLL_MULT and CLK_SEL.

PLL_MULT pin selects the frequency multiplier in the PLL, and

is a standard LVCMOS input. The S pin has an internal pull-up

resistor. The multiplier selection is given on page 2 of this data

sheet (see

Frequency Table).

State Transition Characteristics

Specifies the maximum settling time of the CLK and CLKB

outputs from device power-up. For V

and V

DDX

any

sequences are allowed to power-up and power-down the

CY2XP304.

State Transition Characteristics

From

Transition

Latency

3 ms

Description

Time from V

DDX

applied and settled to

CLK/CLKB outputs settled.

DDX

CLK/CLKB

Normal

Document #: 38-07589 Rev. **

Page 4 of 12

ADVANCE

INFORMATION

Absolute Maximum Conditions

Parameter

VTT

OUT

ESD

ATES

FLM

FIT

Description

Supply Voltage

Operating Voltage

Output Termination Voltage

Input Voltage

Output Voltage

Latch Up Immunity

Temperature, Storage

Temperature, Operating Ambient

Dissipation, Junction to Case

Dissipation, Junction to Ambient

ESD Protection (Human Body Model)

Moisture Sensitivity Level

Total Functional Gate Count

Flammability Rating

Failure in Time

Manufacturing test

Assembled die

Relative to V

Functional

Non-functional

Functional

–65

–40

TBD

2000

TBD

–0.3

300

Condition

Non-functional

Functional

Min.

–0.3

3.135

CY2XP304

Max.

4.6

3.465

– 2

+ 0.3

+150

+85

TBD

Unit

VDC

°C

°C/W

N.A.

Ea.

N.A.

ppm

Crystal Requirements

Requirements to use parallel mode fundamental xtal. External

capacitors are required in the crystal oscillator circuit. Please

refer to the application note entitled

Crystal Oscillator Topics

for details.

Crystal Requirements

Parameter

Frequency

Description

Min.

Max.

31.25

Unit

MHz

DC Electrical Specifications

Parameter

PUP

Supply voltage

Input signal low voltage at pin PLL_MULT

Input signal high voltage at pin PLL_MULT

Internal pull-up resistance

Power-up time for all V

s to reach minimum specified voltage

(power ramps must be monotonic)

Description

Min.

3.135

–

0.65

0.05

Max.

3.465

0.35

–

100

500

Unit

kΩ

Operating Conditions

Parameter

Industrial Temperature

Description

Commercial Temperature

Min.

–40

Max.

Unit

°C

Document #: 38-07589 Rev. **

Page 5 of 12

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CY2XP304BVXC Related Products

	CY2XP304BVXC	CY2XP304BVXI	CY2XP304BVXIT
Description	Clock Generator, 1500MHz, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36	Clock Generator, 1500MHz, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36	Clock Generator, 1500MHz, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-36
Is it Rohs certified?	conform to	conform to	conform to
Maker	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	BGA	BGA	BGA
package instruction	VFBGA,	VFBGA,	VFBGA,
Contacts	36	36	36
Reach Compliance Code	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99
JESD-30 code	R-PBGA-B36	R-PBGA-B36	R-PBGA-B36
JESD-609 code	e1	e1	e1
length	8 mm	8 mm	8 mm
Humidity sensitivity level	3	3	3
Number of terminals	36	36	36
Maximum operating temperature	70 °C	85 °C	85 °C
Minimum operating temperature	-	-40 °C	-40 °C
Maximum output clock frequency	1500 MHz	1500 MHz	1500 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VFBGA	VFBGA	VFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260	260
Master clock/crystal nominal frequency	1500 MHz	1500 MHz	1500 MHz
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1 mm	1 mm	1 mm
Maximum supply voltage	3.465 V	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER
Terminal form	BALL	BALL	BALL
Terminal pitch	0.75 mm	0.75 mm	0.75 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	40	40	40
width	6 mm	6 mm	6 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER

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