DS2182Q+ datasheet, PDF - EEWORLD Datasheet

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DS2182Q+: DescriptionFramer, CMOS, PQCC28, PLASTIC, LCC-28; CategoryWireless rf/communication Telecom circuit; File Size464KB，26 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Environmental Compliance

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DS2182Q+ Overview

Framer, CMOS, PQCC28, PLASTIC, LCC-28

DS2182Q+ Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Maxim
Parts packaging code	QLCC
package instruction	QCCJ,
Contacts	28
Reach Compliance Code	compliant
JESD-30 code	S-PQCC-J28
JESD-609 code	e3
length	11.5062 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	28
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	4.57 mm
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	FRAMER
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	11.5062 mm

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DS2182A

T1 Line Monitor Chip

www.maxim-ic.com

GENERAL DESCRIPTION

The DS2182A T1 line monitor chip is a monolithic

CMOS device designed to monitor real-time

performance on T1 lines. The DS2182A frames to

the data on the line, counts errors, and supplies

detailed information about the status and condition of

the line. Large on-board counters allow the

accumulation of errors for extended periods, which

permits a single CPU to monitor many T1 lines.

Output clocks that are synchronized to the incoming

data stream are provided for easy extraction of

S-bits, FDL bits, signaling bits, and channel data. The

DS2182A meets the requirements of ANSI T1.231.

FEATURES

Performs Framing and Monitoring Functions

Supports Superframe and Extended Superframe

Formats

Four On-Board Error Counters:

16-Bit Bipolar Violation

8-Bit CRC

8-Bit OOF

8-Bit Frame Bit Error

Indication of the Following:

Yellow and Blue Alarms

Incoming B8ZS Codewords

8 and 16 Zero Strings

Change-of-Frame Alignment

Loss of Sync

Carrier Loss

Simple Serial Interface Used for Configuration,

Control, and Status Monitoring

Burst Mode Allows Quick Access to Counters for

Status Updates

Automatic Counter Reset Feature

Single 5V Supply; Low-Power CMOS

Technology

Available in 28-Pin DIP and 28-Pin PLCC

Upward-Compatible from the Original DS2182

ORDERING INFORMATION

PART

DS2182

DS2182N

DS2182Q

DS2182QN

TEMP RANGE

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

PIN-PACKAGE

28 DIP

28 PLCC

PIN CONFIGURATION

TOP VIEW

INT

SDI

SDO

SCLK

N.C.

RYEL

RLINK

RLCLK

RCLK

RCHCLK

RSER

N.C.

DS2182A

RLOS

RFER

RBV

RCL

RNEG

RPOS

RST

TEST

RSIGSEL

RSIGFR

RABCD

RMSYNC

RFSYNC

The DS2182A includes the following changes from

the original DS2182:

Ability to Count Excessive Zeros

Severely Errored-Framing-Event Indication

Updated AIS Detection

Updated RCL Detection

AIS and RCL Alarm Clear Indications

DIP (600 mil)

Note:

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here:

www.maxim-ic.com/errata.

1 of 26

REV: 120103

DS2182A T1 Line Monitor Chip

SERIAL PORT INTERFACE

The port pins of the DS2182A serve as a microprocessor/microcontroller-compatible serial port. Eleven on-board

registers allow the user to update operational characteristics and monitor device status through a host controller,

minimizing hardware interfaces. The port on the DS2182A can be read from or written to at any time. Serial port

reads and writes are independent of T1 line timing signals RCLK, RPOS, and RNEG. However, RCLK is needed to

clear RSR1 and RSR2 after reads.

ADDRESS/COMMAND

Reading or writing the control, configuration, or status registers requires writing one address/command byte prior to

transferring register data. The first bit written (LSB) of the address/command word specifies register read or write.

The following four bits identify the register address. The next two bits are reserved and must be set to 0 for proper

operation. The last bit of the address/ command word enables burst mode when set. The burst mode causes all

registers to be consecutively read or written to. Data is read and written to the DS2182A LSB first.

CHIP SELECT AND CLOCK CONTROL

All data transfers are initiated by driving the

input low. Input data is latched on the rising edge of SCLK and

must be valid during the previous low period of SCLK to prevent momentary corruption of register data during

writes. Data is output on the falling edge of SCLK and held to the next falling edge. All data transfers are

terminated if the

input transitions high. Port control logic is disabled and SDO is tri-stated when

is high.

DATA I/O

Following the eight SCLK cycles that input an address/command byte to write, a data byte is strobed into the

addressed register on the rising edge of the next eight SCLK cycles. Following an address/command word to read,

contents of the selected register are output on the falling edges of the next eight SCLK cycles. The SDO pin is tri-

stated during device write and can be connected to SDI in applications where the host processor has a

bidirectional I/O pin.

BURST MODE

The burst mode allows all on-board registers to be consecutively written to or read by the host processor. A burst

read is used to poll all registers. RSR1 and RSR2 contents are unaffected. This feature minimizes device

initialization time on system power-up or reset. Burst mode is initiated when ACB.7 is set and the address is 0000.

A burst is terminated by a low-high transition on

ACB: Address Command Byte

MSB

NAME

—

ADD3

ADD0

—

POSITION

ACB.7

ACB.6

ACB.5

ACB.4

ACB.1

ACB.0

—

ADD3

ADD2

ADD1

FUNCTION

Burst Mode.

If set (and register address is 0000), burst read or write is

enabled.

Reserved;

must be 0 for operation

Reserved;

must be 0 for operation

MSB of register address

LSB of register address

Read/Write Select

0 = write addressed register

1 = read addressed register

ADD0

LSB

5 of 26

DS2182Q+ Related Products

	DS2182Q+	DS2182Q-	DS2182QN-TR	DS2182Q/T&R	DS2182QN+
Description	Framer, CMOS, PQCC28, PLASTIC, LCC-28		Telecom Interface ICs	Telecom Interface ICs	Telecom Interface ICs
Is it lead-free?	Lead free	-	-	Contains lead	Lead free
Is it Rohs certified?	conform to	-	-	incompatible	conform to
Maker	Maxim	-	-	Maxim	Maxim
Parts packaging code	QLCC	-	-	QLCC	QLCC
package instruction	QCCJ,	-	-	QCCJ,	QCCJ,
Contacts	28	-	-	28	28
Reach Compliance Code	compliant	-	-	compliant	compliant
JESD-30 code	S-PQCC-J28	-	-	S-PQCC-J28	S-PQCC-J28
JESD-609 code	e3	-	-	e0	e3
length	11.5062 mm	-	-	11.505 mm	11.5062 mm
Humidity sensitivity level	1	-	-	1	1
Number of functions	1	-	-	1	1
Number of terminals	28	-	-	28	28
Maximum operating temperature	70 °C	-	-	70 °C	70 °C
Package body material	PLASTIC/EPOXY	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	-	-	QCCJ	QCCJ
Package shape	SQUARE	-	-	SQUARE	SQUARE
Package form	CHIP CARRIER	-	-	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260	-	-	245	260
Certification status	Not Qualified	-	-	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	-	-	4.57 mm	4.57 mm
Nominal supply voltage	5 V	-	-	5 V	5 V
surface mount	YES	-	-	YES	YES
technology	CMOS	-	-	CMOS	CMOS
Telecom integrated circuit types	FRAMER	-	-	FRAMER	FRAMER
Temperature level	COMMERCIAL	-	-	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	-	-	TIN LEAD	Matte Tin (Sn)
Terminal form	J BEND	-	-	J BEND	J BEND
Terminal pitch	1.27 mm	-	-	1.27 mm	1.27 mm
Terminal location	QUAD	-	-	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	-	-	NOT SPECIFIED	NOT SPECIFIED
width	11.5062 mm	-	-	11.505 mm	11.5062 mm

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