DS2182A
T1 Line Monitor Chip
www.maxim-ic.com
GENERAL DESCRIPTION
The DS2182A T1 line monitor chip is a monolithic
CMOS device designed to monitor real-time
performance on T1 lines. The DS2182A frames to
the data on the line, counts errors, and supplies
detailed information about the status and condition of
the line. Large on-board counters allow the
accumulation of errors for extended periods, which
permits a single CPU to monitor many T1 lines.
Output clocks that are synchronized to the incoming
data stream are provided for easy extraction of
S-bits, FDL bits, signaling bits, and channel data. The
DS2182A meets the requirements of ANSI T1.231.
FEATURES
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Performs Framing and Monitoring Functions
Supports Superframe and Extended Superframe
Formats
Four On-Board Error Counters:
16-Bit Bipolar Violation
8-Bit CRC
8-Bit OOF
8-Bit Frame Bit Error
Indication of the Following:
Yellow and Blue Alarms
Incoming B8ZS Codewords
8 and 16 Zero Strings
Change-of-Frame Alignment
Loss of Sync
Carrier Loss
Simple Serial Interface Used for Configuration,
Control, and Status Monitoring
Burst Mode Allows Quick Access to Counters for
Status Updates
Automatic Counter Reset Feature
Single 5V Supply; Low-Power CMOS
Technology
Available in 28-Pin DIP and 28-Pin PLCC
Upward-Compatible from the Original DS2182
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ORDERING INFORMATION
PART
DS2182
DS2182N
DS2182Q
DS2182QN
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
28 DIP
28 DIP
28 PLCC
28 PLCC
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PIN CONFIGURATION
TOP VIEW
INT
SDI
SDO
CS
SCLK
N.C.
RYEL
RLINK
RLCLK
RCLK
RCHCLK
RSER
N.C.
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DS2182A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
RLOS
RFER
RBV
RCL
RNEG
RPOS
RST
TEST
RSIGSEL
RSIGFR
RABCD
RMSYNC
RFSYNC
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The DS2182A includes the following changes from
the original DS2182:
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Ability to Count Excessive Zeros
Severely Errored-Framing-Event Indication
Updated AIS Detection
Updated RCL Detection
AIS and RCL Alarm Clear Indications
DIP (600 mil)
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 120103
DS2182A T1 Line Monitor Chip
Table 1. Pin Description
PIN
1
2
3
4
5
6, 13
7
8
9
10
11
12
15
16
17
18
19
21
22
23
24
25
26
27
NAME
INT
TYPE
O
I
O
I
I
—
O
O
O
I
O
O
O
O
O
O
O
I
I
O
O
O
O
FUNCTION
Receive Alarm Interrupt.
Flags host controller during alarm conditions. Active
low; open-drain output.
Serial Data In.
Data for on-board registers. Sampled on rising edge of SCLK.
Serial Data Out.
Control and status information from on-board registers.
Updated on falling edge of SCLK; tri-stated during serial port write or when CS
is high.
Chip Select.
Must be low to read or write the serial port.
Serial Data Clock.
Used to read or write the serial port registers.
No Connect.
No internal connection. This pin can be connected to either V
SS
or V
DD
, or it can be floated.
Receive Yellow Alarm.
Transitions high when a yellow alarm detected; goes
low when the alarm clears.
Receive Link Data.
Updated with extracted FDL data one RCLK before start
of odd frames (193E) and held until next update. Updated with extracted S-bit
data one RCLK before start of even frames (193S) and held until next update.
Receive Link Clock.
4kHz demand clock for RLINK
Receive Clock.
1.544MHz primary clock
Receive Channel Clock.
192kHz clock; identifies timeslot (channel)
boundaries
Receive Serial Data.
Received NRZ serial data; updated on rising edges of
RCLK
Receive Frame Sync.
Extracted 8kHz clock, one RCLK wide; F-bit position in
each frame
Receive Multiframe Sync.
Extracted multiframe sync; positive-going edge
indicates start of multiframe; 50% duty cycle
Receive ABCD Signaling.
Extracted signaling data output; valid for each
channel in signaling frames. In non-signaling frames, RABCD outputs the LSB
of each channel word.
Receive Signaling Frame.
High during signaling frames; low during non-
signaling frames (and during resync)
Receive Signaling Select.
In 193E framing, a .667kHz clock that identifies
signaling frames A and C; a 1.33kHz clock in 193S
Reset.
A high-low transition clears all internal registers and resets counters. A
high-low-high transition initiates a resync.
Receive Bipolar Data Inputs.
Sampled on falling of RCLK. Connect together
to receive NRZ data and disable bipolar violation monitoring circuitry.
Receive Carrier Loss.
High if 192 consecutive 0’s appear at RPOS and
RNEG; goes low upon seeing 12.5% 1’s density.
Receive Bipolar Violation.
High during accused bit time at RSER. If bipolar
violation detected, low otherwise.
Receive Frame Error.
High during F-bit time when FT or FS errors occur
(193S), or when FPS or CRC errors occur (193E). Low during resync.
Receive Loss-of-Sync.
Indicates sync status; high when internal resync is in
progress, low otherwise.
SDI
SDO
CS
SCLK
N.C.
RYEL
RLINK
RLCLK
RCLK
RCHCLK
RSER
RFSYNC
RMSYNC
RABCD
RSIGFR
RSIGSEL
RST
RPOS
RNEG
RCL
RBV
RFER
RLOS
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DS2182A T1 Line Monitor Chip
Table 2. Power and Test Pin Description
PIN
14
20
28
NAME
V
SS
TEST
V
DD
TYPE
—
I
—
Signal Ground.
0V
Test Mode.
Connect to V
SS
for normal operation.
Positive Supply.
5.0V
FUNCTION
Table 3. Register Summary
REGISTER
BVCR2
BVCR1
CRCCR
OOFCR
FECR
RSR1
RIMR1
RSR2
RIMR2
RCR1
RCR2
ADDRESS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
FUNCTION
Bipolar Violation Count Register 2.
LSW of a 16-bit presettable counter
that records individual bipolar violations.
Bipolar Violation Count Register 1.
MSW of a 16-bit presettable counter
that records individual bipolar violations.
CRC Error Count Register.
8-bit presettable counter that records CRC6
errored words in the 193E frame mode.
OOF Count Register.
8-bit presettable counter that records OOF events.
OOF events are defined by RCR1.5 and RCR1.6.
Frame Error Count Register.
8-bit presettable counter that records
individual bit errors in the framing pattern.
Receive Status Register 1.
Reports alarm conditions.
Receive Interrupt Mask Register 1.
Allows masking of individual alarm-
generated interrupts from RSR1.
Receive Status Register 2.
Reports alarm conditions.
Receive Interrupt Mask Register 2.
Allows masking of individual alarm-
generated interrupts from RSR2.
Receive Control Register 1.
Programs device operating characteristics.
Receive Control Register 2.
Programs device operating characteristics.
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DS2182A T1 Line Monitor Chip
Figure 1. Block Diagram
Dallas
Semiconductor
DS2182A
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DS2182A T1 Line Monitor Chip
SERIAL PORT INTERFACE
The port pins of the DS2182A serve as a microprocessor/microcontroller-compatible serial port. Eleven on-board
registers allow the user to update operational characteristics and monitor device status through a host controller,
minimizing hardware interfaces. The port on the DS2182A can be read from or written to at any time. Serial port
reads and writes are independent of T1 line timing signals RCLK, RPOS, and RNEG. However, RCLK is needed to
clear RSR1 and RSR2 after reads.
ADDRESS/COMMAND
Reading or writing the control, configuration, or status registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSB) of the address/command word specifies register read or write.
The following four bits identify the register address. The next two bits are reserved and must be set to 0 for proper
operation. The last bit of the address/ command word enables burst mode when set. The burst mode causes all
registers to be consecutively read or written to. Data is read and written to the DS2182A LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the
CS
input low. Input data is latched on the rising edge of SCLK and
must be valid during the previous low period of SCLK to prevent momentary corruption of register data during
writes. Data is output on the falling edge of SCLK and held to the next falling edge. All data transfers are
terminated if the
CS
input transitions high. Port control logic is disabled and SDO is tri-stated when
CS
is high.
DATA I/O
Following the eight SCLK cycles that input an address/command byte to write, a data byte is strobed into the
addressed register on the rising edge of the next eight SCLK cycles. Following an address/command word to read,
contents of the selected register are output on the falling edges of the next eight SCLK cycles. The SDO pin is tri-
stated during device write and can be connected to SDI in applications where the host processor has a
bidirectional I/O pin.
BURST MODE
The burst mode allows all on-board registers to be consecutively written to or read by the host processor. A burst
read is used to poll all registers. RSR1 and RSR2 contents are unaffected. This feature minimizes device
initialization time on system power-up or reset. Burst mode is initiated when ACB.7 is set and the address is 0000.
A burst is terminated by a low-high transition on
CS
.
ACB: Address Command Byte
MSB
BM
NAME
BM
—
—
ADD3
ADD0
R/
W
—
POSITION
ACB.7
ACB.6
ACB.5
ACB.4
ACB.1
ACB.0
—
ADD3
ADD2
ADD1
FUNCTION
Burst Mode.
If set (and register address is 0000), burst read or write is
enabled.
Reserved;
must be 0 for operation
Reserved;
must be 0 for operation
MSB of register address
LSB of register address
Read/Write Select
0 = write addressed register
1 = read addressed register
ADD0
LSB
R/
W
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