pled to a LC optical connector. Its small size allows for high-density board designs
that, in turn, enable greater total aggregate bandwidth.
Highlights
• 4GFC, 2GFC, and 1GFC and 1GbE multiple rate performance enables flexible
system design, and configuration, while maximizing bandwidth
• RoHS-compliant per Directive 2002/95/EC
• Enhanced digital diagnostic feature set allows real-time monitoring of
transceiver performance and system stability.
• Bail mechanism enables superior ergonomics and functionality in all port configurations
• Extended/Industrial voltage and extended temperature
• MSA-compliant small form factor footprint enables high port density and keeps
overall system cost low
• Serial ID allows customer and vendor system specific information to be placed
in transceiver
• All-metal housing provides superior EMI performance
NORTH AMERICA: 800 498-JDSU (5378)
WORLDWIDE: +800 5378-JDSU
WEBSITE: www.jdsu.com
ROHS-COMPLIANT 4.25, 2.125, 1.25, 1.0625 GBPS
850 NM SFP TRANSCEIVER
2
Features
• Uses a JDSU high-reliability, high-
speed, 850 nm, oxide VCSEL
• RoHS-compliant
• Hot pluggable
• Digital diagnostics, SFF-8472 rev 9.5
compliant
• Compliant with Fibre Channel
400-M5/M6-SN-1, 200-M5/M6-SN-I,
100-M5/M6-SN-I and 1000Base-SX
• Selectable 4G/2G/1G receiver
bandwidth with rate select pin 7 or
through digital diagnostics interface
• Low nominal power consumption
(< 400 mW)
• -20˚C to 85˚C operating temperature
range for PLRXPL-VE-SG4-38
• Single +3.3 V power supply
• ±10% extended operating voltage range
• Bit error rate < 1 x 10
-12
• OC transmit disable, loss of signal
and transmitter fault functions
• CDRH and IEC 60825-1 Class 1 laser
eye safe
• FCC Class B compliant
• ESD Class 2 per MIL-STD 883
Method 3015
• UL-94 V-0 certified
• Internal AC coupling on both transmit
and receive data signals
An eye-safe, cost effective serial transceiver, the PLRXPL-VE-SG4-38 features a small,
low power, pluggable package that manufacturers can upgrade in the field, adding
bandwidth incrementally. The robust mechanical design features a unique all-metal
housing that provides superior EMI shielding.
ROHS-COMPLIANT 4.25, 2.125, 1.25, 1.0625 GBPS
850 NM SFP TRANSCEIVER
3
Section 1
Functional Description
The PLRXPL-VE-SG4-38 850 nm VCSEL Gigabit Transceiver is designed to trans-
mit and receive 8B/10B or 64B/66B encoded serial optical data over 50/125 µm
or 62.5/125 µm multimode optical fiber. This transceiver is RoHS-compliant per
Directive 2002/95/EC.
Transmitter
The transmitter converts 8B/10B or 64B/66B encoded serial PECL or CML electri-
cal data into serial optical data meeting the requirements of 100-M5/M6-SN-I,
200-M5/M6-SN-I, 400-M5/M6-SN-I Fibre Channel and 1000Base-SX Ethernet
specifications. Transmit data lines (TD+ & TD-) are internally AC coupled with
100
Ω
differential termination.
An open collector compatible Transmit Disable (Tx_Dis) is provided. This pin is
internally terminated with a 10 kΩ resistor to Vcc
T
. A logic “1,” or no connection
on this pin will disable the laser from transmitting. A logic “0” on this pin provides
normal operation.
The transmitter has an internal PIN monitor diode that is used to ensure constant
optical power output across supply voltage and temperature variations.
An open collector compatible Transmit Fault (TFault) is provided. The Transmit Fault
signal must be pulled high on the host board for proper operation. A logic “1” output
from this pin indicates that a transmitter fault has occurred, or the part is not fully seat-
ed and the transmitter is disabled. A logic “0” on this pin indicates normal operation.
The extinction ratio of the transmitter is automatically increased to meet the re-
quirements of 1000BASE-SX Ethernet specifications when the Rate Select pin and
software bit are set to “low”.
Receiver
The receiver converts 8B/10B or 64B/66B encoded serial optical data into serial
PECL/CML electrical data. Receive data lines (RD+ and RD-) are internally AC
coupled with 100
Ω
differential source impedance, and must be terminated with
a 100
Ω
differential load.
Rate select, pin 7, switches the receiver bandwith enabling superior performance
at 4.25 Gbps, 2.125 Gbps, 1.25 and 1.0625 Gbps line rates. When rate-select is set
“high” (4.25/2.125 Gbps mode) the receiver bandwidth is not compliant to the
maximum receiver bandwidth specified under 100-M5/M6-SN-I.
Table 1 FC Compliance with Rate Select
Parameter
High
Low
1. Not compliant to receiver bandwidth
2. Also 1000Base-SX compliant
100-M5/M6-SN-I
No
1
Yes
2
200-M5/M6-SN-I
Yes
Yes
400-M5/M6-SN-I
Yes
No
1
ROHS-COMPLIANT 4.25, 2.125, 1.25, 1.0625 GBPS
850 NM SFP TRANSCEIVER
4
An open collector compatible Loss of Signal is provided. The LOS must be pulled
high on the host board for proper operation. A logic “0” indicates that light has
been detected at the input to the receiver (see Section 2.5 Optical characteristic,
Loss of Signal Assert/Deassert Time on page 9). A logic “1” output indicates that
insufficient light has been detected for proper operation.
Power supply filtering is recommended for both the transmitter and receiver. Fil-
tering should be placed on the host assembly as close to the Vcc pins as possible
for optimal performance.
Recommended “Application Schematics” are shown in Figure 2 on page 5.
16 Transmitter Power Supply
10K
Ω
3 Transmitter Disable In
Vcc_T
Vcc_T
TDis
TD+
18 Transmitter
Positive Data In
50
Ω
TOSA
Laser Driver
50
Ω
TD-
T_Gnd
T_Fault
19 Transmitter
Negative Data In
2 Transmitter Fault Out
1, 17, 20 Transmitter
Signal Ground
Management
SCL
Processor
EEPROM
5 MOD_DEF(1) Serial ID Clock
4 MOD_DEF(2) Serial ID Data
6 MOD_DEF(0)
15 Receiver Power Supply
SDA
Vcc_R
Vcc_R
RD-
50
Ω
ROSA
R_Gnd
RECEIVER
50
Ω
RD+
R_Gnd
LOS
12 Receiver Negative
Data Out
13 Receiver Positive
Data Out
7 Rate Select
30 kΩ
8 Loss of Signal Out
9, 10, 11, 14 Receiver
Signal Ground
Figure 1
Block diagram
ROHS-COMPLIANT 4.25, 2.125, 1.25, 1.0625 GBPS
850 NM SFP TRANSCEIVER
5
Section 2
Application Schematics
Recommended connections to the PLRXPL-VE-SG4-38 transceiver are shown in
Figure 2 below.
10K
Receiver (Tx Fault)
Open Collector
Driver (Tx Disable)
R1
*
50
Z = 100
*
PECL
Driver
(TX DATA)
SFP Host Connector
10K
1 VeeT
2 Tx Fault
10K
3 Tx Disable
4 MOD_DEF(2)
5 MOD_DEF(1)
10K
6 MOD_DEF(0)
7 Rate select
8 LOS
9 VeeR
VeeT 20
TD- 19
TD+ 18
VeeT 17
VccT 16
VccR 15
VeeR 14
RD+ 13
RD- 12
VeeR 11
C4
Open Collector
Bidirectional
{Mod_Def(2)}
R2
*
50
C3
0.1 F
L1
1 H
C2
L2
1 H
C5
10
u
F
0.1 F
C1
10 F
+3.3V
Vcc
Input
Open Collector
Bidirectional
{Mod_Def(1)}
Receiver
{Mod_Def(0)}
0.1uF
Receiver and
Transmitter
Rate Select
10 VeeR
10K
Receiver (LOS)
Z = 100
*
R3
50
*
PECL
Receiver
(RX DATA)
R4
*
50
Notes
Power supply filtering components should be placed as close to the V
cc
pins of the host connector as possible for optimal performance.
PECL driver and receiver will require biasing networks. Please consult application notes from suppliers of these components. CML I/O on the PHY are supported.
MOD_DEF(2) and MOD_DEF(1) should be bi-directional open collector connections in order to implement serial ID (MOD_DEF[0,1,1]) PLRXPL-VE-SG4-38 transceiver.
R1 and R2 may be included in the output of the PHY. Check application notes of the IC in use.
* Transmission lines should be 100
Ω
differential traces. It is recommended that the termination resistor for the PECL Receiver (R3 + R4) be placed beyond the input pins of the
PECL Receiver. Series Source Termination Resistors on the PECL Driver (R1+R2) should be placed as close to the driver output pins as possible
Figure 2
Recommended application schematic for the PLRXPL-VE-SG4-38 transceiver
京公网安备 11010802033920号
EEWORLD
