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PERFORMANCE FEATURES
12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sus-
tained performance
Single-cycle instruction execution
Single-cycle context switch
3-bus architecture allows dual operand fetches in every
instruction cycle
Multifunction instructions
Power-down mode featuring low CMOS standby power dissi-
pation with 200 CLKIN cycle recovery from power-down
condition
Low power dissipation in idle mode
DSP Microcomputer
ADSP-218xN Series
SYSTEM INTERFACE FEATURES
Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation
All inputs tolerate up to 3.6 V regardless of mode
16-bit internal DMA port for high-speed access to on-chip
memory (mode selectable)
4M-byte memory interface for storage of data tables and pro-
gram overlays (mode selectable)
8-bit DMA to byte memory for transparent program and data
memory transfers (mode selectable)
Programmable memory strobe and separate I/O memory
space permits “glueless” system design
Programmable wait state generation
Two double-buffered serial ports with companding hardware
and automatic data buffering
Automatic booting of on-chip program memory from byte-
wide external memory, for example, EPROM, or through
internal DMA Port
Six external interrupts
13 programmable flag pins provide flexible system signaling
UART emulation through software SPORT reconfiguration
ICE-Port™ emulator interface supports debugging in final
systems
INTEGRATION FEATURES
ADSP-2100 family code compatible (easy to use algebraic
syntax), with instruction set extensions
Up to 256K byte of on-chip RAM, configured
Up to 48K words program memory RAM
Up to 56K words data memory RAM
Dual-purpose program memory for both instruction and
data storage
Independent ALU, multiplier/accumulator, and barrel shifter
computational units
Two independent data address generators
Powerful program sequencer provides zero overhead loop-
ing conditional instruction execution
Programmable 16-bit interval timer with prescaler
100-lead LQFP and 144-ball BGA
PO W E R-DO WN
C ONTR O L
FU L L M EM O R Y M O D E
M EM OR Y
D A T A A D D RES S
G ENERAT OR S
D A G1
D AG2
PROG RAM
SEQ U ENCER
PRO GRA M
ME M ORY
UP TO
48K
24-B IT
D A TA
ME M ORY
UP TO
56K
16-B IT
PROG RA MM ABL E
I/O
AND
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EX TE RNAL
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A R ITH M ETIC UN ITS
A LU
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S H IFTE R
S ER IAL PO R TS
S POR T0
SPOR T 1
A DS P-2100 B AS E
A RC H IT EC T UR E
Figure 1. Functional Block Diagram
ICE-Port is a trademark of Analog Devices, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
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Fax: 781.461.3113
© 2006 Analog Devices, Inc. All rights reserved.
ADSP-218xN
TABLE OF CONTENTS
General Description ................................................. 3
Architecture Overview ........................................... 3
Modes Of Operation .............................................. 5
Interrupts ........................................................... 5
Low-power Operation ............................................ 6
System Interface ................................................... 7
Reset .................................................................. 8
Power Supplies ..................................................... 8
Memory Architecture ............................................ 9
Bus Request and Bus Grant ................................... 14
Flag I/O Pins ..................................................... 15
Instruction Set Description ................................... 15
Development System ........................................... 15
Additional Information ........................................ 17
Pin Descriptions .................................................... 18
Memory Interface Pins ......................................... 19
Terminating Unused Pins ..................................... 19
Specifications ........................................................ 22
Recommended Operating Conditions ...................... 22
Electrical Characteristics ....................................... 22
Absolute Maximum Ratings .................................. 23
ESD Sensitivity ................................................... 23
ESD Diode Protection .......................................... 24
Power Dissipation ............................................... 24
Environmental Conditions .................................... 25
Test Conditions .................................................. 25
Timing Specifications .......................................... 26
LQFP Package Pinout .......................................... 40
BGA Package Pinout ........................................... 42
Outline Dimensions ............................................... 45
Surface Mount Design .......................................... 46
Ordering Guide ..................................................... 47
REVISION HISTORY
8/06—Rev. 0 to Rev. A
Miscellaneous Format Updates.......................... Universal
Applied Corrections or Additional Information to:
Clock Signals ....................................................... 8
External Crystal Connections .................................. 8
ADSP-2185 Memory Architecture ............................ 9
Electrical Characteristics ....................................... 22
Absolute Maximum Ratings ................................... 23
ESD Diode Protection .......................................... 24
Memory Read ..................................................... 31
Memory Write .................................................... 32
Serial Ports ........................................................ 33
Outline Dimensions ............................................. 45
Ordering Guide .................................................. 47
Rev. A |
Page 2 of 48 |
August 2006
ADSP-218xN
GENERAL DESCRIPTION
The ADSP-218xN series consists of six single chip microcom-
puters optimized for digital signal processing applications. The
high-level block diagram for the ADSP-218xN series members
appears on the previous page. All series members are pin-com-
patible and are differentiated solely by the amount of on-chip
SRAM. This feature, combined with ADSP-21xx code compati-
bility, provides a great deal of flexibility in the design decision.
Specific family members are shown in
Table 1.
Table 1. ADSP-218xN DSP Microcomputer Family
Device
ADSP-2184N
ADSP-2185N
ADSP-2186N
ADSP-2187N
ADSP-2188N
ADSP-2189N
Program Memory
(K words)
4
16
8
32
48
32
Data Memory
(K words)
4
16
8
32
56
48
• Receive and/or transmit data through the byte DMA port
• Decrement timer
ARCHITECTURE OVERVIEW
The ADSP-218xN series instruction set provides flexible data
moves and multifunction (one or two data moves with a com-
putation) instructions. Every instruction can be executed in a
single processor cycle. The ADSP-218xN assembly language
uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development.
The functional block diagram is an overall block diagram of the
ADSP-218xN series. The processor contains three independent
computational units: the ALU, the multiplier/accumulator
(MAC), and the shifter. The computational units process 16-bit
data directly and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, and multi-
ply/subtract operations with 40 bits of accumulation. The shifter
performs logical and arithmetic shifts, normalization, denor-
malization, and derive exponent operations.
The shifter can be used to efficiently implement numeric format
control, including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps,
subroutine calls, and returns in a single cycle. With internal
loop counters and loop stacks, ADSP-218xN series members
execute looped code with zero overhead; no explicit jump
instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and pro-
gram memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possi-
ble modify registers. A length value may be associated with each
pointer to implement automatic modulo addressing for
circular buffers.
Five internal buses provide efficient data transfer:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
ADSP-218xN series members combine the ADSP-2100 family
base architecture (three computational units, data address gen-
erators, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
ADSP-218xN series members integrate up to 256K bytes of on-
chip memory configured as up to 48K words (24-bit) of pro-
gram RAM, and up to 56K words (16-bit) of data RAM. Power-
down circuitry is also provided to meet the low power needs of
battery-operated portable equipment. The ADSP-218xN is
available in a 100-lead LQFP package and 144-ball BGA.
Fabricated in a high-speed, low-power, 0.18 μm CMOS process,
ADSP-218xN series members operate with a 12.5 ns instruction
cycle time. Every instruction can execute in a single pro-
cessor cycle.
The ADSP-218xN’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle, ADSP-218xN series
members can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal
DMA port
Rev. A |
Page 3 of 48 |
August 2006
ADSP-218xN
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting ADSP-218xN series members to fetch two operands in a
single cycle, one from program memory and one from data
memory. ADSP-218xN series members can fetch an operand
from program memory and the next instruction in the
same cycle.
In lieu of the address and data bus for external memory connec-
tion, ADSP-218xN series members may be configured for 16-bit
Internal DMA port (IDMA port) connection to external sys-
tems. The IDMA port is made up of 16 data/address pins and
five control pins. The IDMA port provides transparent, direct
access to the DSP’s on-chip program and data RAM.
An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
grammable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH, and BG). One execution mode (Go Mode) allows the
ADSP-218xN to continue running from on-chip memory. Nor-
mal execution mode requires the processor to halt while buses
are granted.
ADSP-218xN series members can respond to eleven interrupts.
There can be up to six external interrupts (one edge-sensitive,
two level-sensitive, and three configurable) and seven internal
interrupts generated by the timer, the serial ports (SPORT), the
BDMA port, and the power-down circuitry. There is also a mas-
ter RESET signal. The two serial ports provide a complete
synchronous serial interface with optional companding in hard-
ware and a wide variety of framed or frameless data transmit
and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
ADSP-218xN series members provide up to 13 general-purpose
flag pins. The data input and output pins on SPORT1 can be
alternatively configured as an input flag and an output flag. In
addition, eight flags are programmable as inputs or outputs, and
three flags are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
ADSP-218xN series members incorporate two complete syn-
chronous serial ports (SPORT0 and SPORT1) for serial
communications and multiprocessor communication.
Following is a brief list of the capabilities of the ADSP-218xN
SPORTs. For additional information on Serial Ports, refer to the
ADSP-218x DSP Hardware Reference.
• SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and
transmit sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally gen-
erated. Frame sync signals are active high or inverted, with
either of two pulsewidths and timings.
• SPORTs support serial data word lengths from 3 bits to
16 bits and provide optional A-law and
μ-law
companding,
according to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer
of data with only one overhead cycle per data word. An
interrupt is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 word or 32-word, time-division multi-
plexed, serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the FI and FO signals. The internally
generated serial clock may still be used in this
configuration.
Rev. A |
Page 4 of 48 |
August 2006
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