Application of millimeter wave radar technology in corner radar

In recent years, millimeter wave radar technology has become increasingly mature. In the industrial field, we mainly introduced the application of barrier radars. In the automotive field, the main radar applications can be roughly divided into two categories: corner radars and front radars.

Corner radars (including forward corner radars and rear corner radars) are generally short-range radars that meet the requirements of blind spot detection (BSD), lane change assist (LCA) and front and rear traffic alert (F/RCTA); while forward radars are mainly medium- and long-range radar applications for autonomous emergency braking (AEB) and adaptive cruise control (ACC).

Traditional corner radar is mainly based on 24 GHz technology, but due to emerging regulatory requirements and the need for higher bandwidth, smaller size and higher performance, corner radar is gradually moving to the 77 GHz band.

This chapter will introduce the short-range radar solution for corner radar based on AWR1642. Since the system block diagram is similar to the previous barrier radar, the main differences are three points: first, the radar chip uses AWR1642; second, the interface chip is a CAN interface commonly used in automobiles; third, in order to make the RF power supply rail cleaner, a first-level LDO is used for filtering before powering the on-board radar chip.

Figure 1 System block diagram of corner radar application

The following will be a detailed discussion of AWR1642.

High-level architecture of the AWR1642

AWR1642 is a highly integrated single-chip 77 GHz millimeter wave radar, which includes two transmitters and four receivers, a 600 MHz programmable C674x DSP, and a 200 MHz programmable ARM Cortex-R4F processor. The device supports RF bandwidth, covering 76-77 GHz and 77-81 GHz frequency bands. As shown in Figure 2, the device includes four main modules: RF/analog front-end subsystem, BIST subsystem, DSP subsystem, and main control subsystem.

Figure 2 High-level architecture of the AWR1642

The RF/Analog Front-End subsystem includes the RF and analog circuits: synthesizer, power amplifier (PAS), low noise amplifier (LNA), mixer, intermediate frequency (IF) link, and analog-to-digital converter (ADC). This subsystem also includes a crystal oscillator, temperature sensor, voltage monitor, and general-purpose ADC. The AWR1642 device uses a complex baseband architecture that provides in-phase (I channel) and quadrature (Q channel) outputs.

The built-in self-test subsystem, also known as the BIST subsystem, includes the digital front end, ramp generator, and an internal processor that controls and configures the low-level RF analog circuitry and registers of the ramp generator. (Note: This processor is programmed by TI to handle RF calibration needs and BIST/monitoring functions, but it is not directly available to the user.) The digital front end is responsible for filtering and decimating the raw ADC output and providing the final ADC data samples at a programmable sampling rate.

The DSP subsystem includes a TI C674x DSP with a clock frequency of 600 MHz, which is used for radar signal processing, usually processing raw ADC data. The DSP is user programmable and has complete flexibility in use.

The main control subsystem includes an ARM automotive-grade Cortex-R4F processor with a main frequency of 200MHz, which is user-programmable. This processor controls the overall operation of the device, handles the communication interface, and implements higher-level algorithms such as target classification and tracking. The processor can also run the AUTOSAR system.

The AWR1642 can be used for short-range radar (SRR) applications. The device includes a QSPI interface to download user code directly from serial flash memory; it also includes CAN-FD and CAN interfaces, so it can communicate directly with other sensors on the vehicle CAN bus or a dedicated CAN bus; it can also control the PMIC using the SPI/I2C interface.

The total available memory of the AWR1642 is 1.5 MB. It supports partitioning between R4F program RAM, R4F data RAM, DSP L1 and L2 memory, and radar data memory (L3 memory). Table 1 lists some example memory configurations.

Table-1 Memory Configuration Example

The L2 memory in the DSP subsystem is 256 KB, which is usually used for instructions and immediate data of DSP applications. The DSP subsystem also includes 32 KB of L1 memory and data RAM, which can be configured as cache in whole or in part.

The R4F has 448 KB of dedicated memory that is divided between the R4F tightly coupled memory interface TCMA (256 KB) and TCMB (192 KB). Although the full 448 KB of memory is not set up and can be used for instructions or data, a typical application will use TCMA as instruction memory and TCMB as data memory.

The remaining 768 KB is L3 memory, which can be used as radar data volume memory. Up to 512 KB of L3 memory can be shared with the R4F in 128 KB increments.

DSP Advantages

One of the key advantages of the AWR1642 is its built-in C674x DSP. Frequency modulated continuous wave (FMCW) radar technology has made great progress in the past few years. Radar plays a more important role in current vehicles, not only in terms of driver comfort, but also in terms of safety. These applications also place more stringent performance requirements on radar in terms of spatial resolution, velocity resolution, and target detection and classification.

The fully programmable DSP in the AWR1642 enables customers to implement proprietary algorithms and build innovative solutions to address challenging radar performance challenges. Research and advancements around algorithms are continuing to improve performance in several key areas, such as:

Interference Mitigation: As more and more vehicles adopt radar technology, the problem of interference between radars becomes more and more serious. In this context, innovative algorithms for detecting and mitigating interference are an active area of ​​research and signal processing algorithm development.

Improved detection algorithms: Emerging applications of radar, including the ultimate vision for fully autonomous driving, necessitate improved algorithms related to target detection, ground clutter removal, and minimizing false detections to ensure stability.

High-resolution angle estimation: One of the main challenges associated with radar is the limited angle resolution. Several advanced angle estimation algorithms beyond conventional beamforming can improve the angle resolution, including signal classification through rotational invariance techniques (ESPIRIT) (MUSIC) and signal parameter estimation.

Clustering and object classification algorithms: This is another active area of ​​research and algorithm development, especially object classification algorithms that require the use of high-resolution radar point clouds and the identification of pedestrians using micro-Doppler techniques.

To meet these requirements, the built-in DSP implements high-performance and fully programmable signal processing capabilities. Table 2 provides benchmark data on DSP performance in some typical radar signal processing routines.

Table - 2 Benchmark data for common radar signal processing routines

Encryption security

AWR1642 provides a secure boot mechanism. Secure boot is a security enabler that provides mechanisms to help keep code algorithms in an encrypted form and help prevent unauthorized access. Also, it helps avoid rogue code from being implanted on the device, thereby preventing the device from running altered code/functionality.

To speed up the computationally intensive encoding and decoding processes, the AWR1642 is equipped with hardware-based accelerator security features that can also be used by applications for additional security.

Advanced Encryption Standard (AES).

Secure Hash Accelerator (SHA2).

True Random Number Generator (TRNG).

Public Key Accelerator (PKA).

In addition, the AWR1642 provides a secure debugging mechanism that makes the debugging process hassle-free while helping to protect the device from various threats.

Safety

The AWR1642 is part of the TI SafeTI™ design suite, which helps developers implement ISO26262 ASILB level functional safety in their applications.

The AWR1642 follows a concept called "Safety Island," which involves a balance between the application of hardware diagnostics and software diagnostics to help manage functional safety. It fully tests a set of core elements at power-up and monitors them closely to help provide correct software execution. This core element set includes power, clocks, resets, R4F processors, and associated program and data memory to help execute software, enabling software-based diagnostics on other elements such as peripherals.

The device also includes advanced built-in circuitry for monitoring the RF and analog front-end circuits, a dedicated processor (delayed lock-step) core running TI firmware helps simplify application development, and is fully capable of enabling DSPs and MCUs to extract millions of instructions per second (MIPS) from any kind of radar front-end monitoring.

The AWR1642 sensor supports the following front-end diagnostic functions:

Synthesizer LFM Monitor.

TX output power monitor.

RF loopback based noise figure, gain imbalance and phase imbalance monitor.

RX saturation monitor.

IF amplifier (IFA) jitter attenuation monitor based on IF loopback.

Ball-break monitor.

Temperature sensor.

Other key diagnostic features include logic BIST for the central processing unit (CPU) core, memory BIST for all memories, windowed watchdog for each processor, end-to-end error correction code, memory protection unit, clock and power monitors, fault fluctuation on reset, and an error signaling module.

These features help make it easier and faster for developers to achieve ASIL-B functional safety. Safety-critical development requires managing both systematic and random failures. TI has created a unique development process for safety-critical semiconductors, customizing the functional safety lifecycle of ISO 26262:2011 to most effectively address the needs of a non-safety environment (SEooC). This development process has been certified by independent third-party auditor TÜV SÜD.