Advanced Information
CAT93CXXXX (1K-16K)
Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
FEATURES
s
Watchdog Timer
s
Programmable Reset Threshold
s
Built-in Inadvertent Write Protection
s
Active High or Low Reset Outputs
—Precision Power Supply Voltage Monitoring
—5V, 3.3V and 3V options
s
Hardware and Software Write Protection
s
Power-Up Inadvertant Write Protection
s
1,000,000 Program/Erase Cycles
s
100 Year Data Retention
s
Commercial, Industrial, and Automotive
—V
CC
Lock Out
s
High Speed Operation: 3MHz
s
Low Power CMOS Technology
s
x 16 or x 8 Selectable Serial Memory
s
Self-Timed Write Cycle with Auto-Clear
s
Sequential Read
s
Fast Nonvolatile Write Cycle: 3ms Max
Temperature Ranges
s
2.7-6.0 Volt Operation
s
16 Byte Page Mode
DESCRIPTION
The CAT93CXXXX is a single chip solution to three
popular functions of EEPROM memory, precision reset
controller and watchdog timer. The serial EEPROM
memory of the 93CXXXX can be configured either by 16-
bits or by 8-bits. Each register can be written (or read)
by using the DI (or DO pin).
The reset function of the 93CXXXX protects the system
during brown out and power up/down conditions. During
system failure the watchdog timer feature protects the
microcontroller with a reset signal. Catalyst's advanced
CMOS technology substantially reduces device power
requirements. The 93CXXXX is available in 8-pin DIP, 8-
pin TSSOP or 8-pin SOIC packages. It is designed to
endure 1,000,000 program/erase cycles and has a data
retention of 100 years.
PIN CONFIGURATION
93CX61X
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
CS
RESET(RESET) SK
ORG
DI
GND
DO
BLOCK DIAGRAM
93CX63X
VCC
CS
RESET(RESET) SK
WDI
DI
GND
DO
1
2
3
4
8
7
6
5
VCC
RESET
RESET
GND
93CX62X
1
2
3
4
8
7
6
5
VCC
GND
PIN FUNCTIONS
Pin Name
CS
RESET/RESET
SK
DI
DO
V
CC
GND
ORG
Function
Chip Select
Reset I/O
Clock Input
Serial Data Input
ORG
MEMORY ARRAY
ADDRESS
DECODER
DATA
REGISTER
DI
MODE DECODE
LOGIC
OUTPUT
BUFFER
CS
Serial Data Output
+2.7 to 6.0V Power Supply
Ground
Memory Organization
SK
CLOCK
GENERATOR
DO
RESET Controller
WATCHDOG
High
Precision
Vcc Monitor
Note: When the ORG pin is connected to VCC, the X16 organiza
tion is selected. When it is connected to ground, the X8 pin
is selected. If the ORG pin is left unconnected, then an
internal pullup device will select the X16 organization.
WDI RESET/RESET
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9-85
CAT93CXXXX
Advanced Information
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias....................–55°C to +125°C
Storage Temperature........................ –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
..............–2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground..................–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)1.0W.................................1.0W
Lead Soldering Temperature (10 secs)...............300°C
Output Short Circuit Current
(2)
..........................100mA
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.7V to +6.0V, unless otherwise specified.
Limits
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
OL1
V
OH1
Parameter
Power Supply Current
(Write)
Power Supply Current
(Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
Input Leakage Current
Output Leakage Current
(Including ORG pin)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
2.4
V
-0.1
2
Min.
Typ.
Max.
3
1
10
0
1
1
0.8
V
CC
+1
0.4
Units
mA
mA
µA
µA
µA
µA
V
V
V
4.5V≤V
CC
<5.5V
I
OL
= 2.1mA
I
OH
= -400µA
Test Conditions
f
SK
= 1MHz
V
CC
= 5.0V
f
SK
= 1MHz
V
CC
= 5.0V
CS = 0V
ORG=GND
CS=0V
ORG=Float or V
CC
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
,
CS = 0V
4.5V≤V
CC
<5.5V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
Stock No. 21084-01 2/98
9-86
Advanced Information
CAT93CXXXX
RELIABILITY CHARACTERISTICS
Symbol
N
END(1)
T
DR(1)
V
ZAP(1)
I
LTH(1)(3)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
1,000,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
A.C. CHARACTERISTICS
V
CC
=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF
Limits
V
CC
=
2.7V -6V
SYMBOL PARAMETER
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(1)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
0.5
0.5
0.5
0.5
1000
DC
Min.
250
0
250
250
0.5
0.5
500
5
0.1
0.1
0.1
0.1
3000
Max.
V
CC
=
4.5V-5.5V
Min.
50
0
50
50
0.1
0.1
100
5
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
KHZ
C
L
= 100pF
Test
Max. UNITS Conditions
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(1)
C
IN(1)
Test
Input/Output Capacitance
Input Capacitance
Max.
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
9-87
Stock No. 21084-01 2/98
CAT93CXXXX
INSTRUCTION SET
Instruction Device
Type
READ
93C46XX
93C56XX
(1)
93C66XX
93C57XX
93C86XX
93C46XX
93C56XX
(1)
93C66XX
93C57XX
93C86XX
93C46XX
93C56XX
(1)
93C66XX
93C57XX
93C86XX
93C46XX
93C56XX
93C66XX
93C57XX
93C86XX
93C46XX
93C56XX
93C66XX
93C57XX
93C86XX
93C46XX
93C56XX
93C66XX
93C57XX
93C86XX
93C46XX
93C56XX
93C66XX
93C57XX
93C86XX
Start Opcode
Bit
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
10
10
10
10
10
11
11
11
11
11
01
01
01
01
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Address
x8
x16
A6–A0
A8–A0
A8–A0
A7-A0
A10-A0
A6–A0
A8–A0
A8–A0
A7-A0
A10-A0
A6–A0
A8–A0
A8–A0
A7-A0
A10-A0
A5-A0
A7-A0
A7-A0
A6-A0
A9-A0
A5-A0
A7-A0
A7-A0
A6-A0
A9-A0
A5-A0
A7-A0
A7-A0
A6-A0
A9-A0
D7-D0
D7-D0
D7-D0
D7-D0
D7-D0
D15-D0
D15-D0
D15-D0
D15-D0
D15-D0
Data
x8
x16
Advanced Information
Comments
Read Address AN–A0
ERASE
Clear Address AN–A0
WRITE
Write Address AN–A0
EWEN
11XXXXX
11XXXX
11XXXXXXX
11XXXXXX
11XXXXXXX
11XXXXXX
11XXXXXX
11XXXXX
11XXXXXXXXX 11XXXXXXXX
00XXXXX
00XXXXXXX
00XXXX
00XXXXXX
Write Enable
EWDS
Write Disable
00XXXXXXX
00XXXXXX
00XXXXXX
00XXXXX
00XXXXXXXXX 00XXXXXXXX
10XXXXX
10XXXXXXX
10XXXXXXX
10XXXXXX
10XXXX
10XXXXXX
10XXXXXX
10XXXXX
ERAL
Clear All Addresses
10XXXXXXXXX 10XXXXXXXX
01XXXXX
01XXXXXXX
01XXXXXXX
01XXXXXX
01XXXX
01XXXXXX
01XXXXXX
01XXXXX
WRAL
01XXXXXXXXX 01XXXXXXXX
D7-D0
D7-D0
D7-D0
D7-D0
D7-D0
D15-D0
D15-D0
D15-D0
D15-D0
D15-D0
Write All Addresses
Note:
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE and
ERASE commands.
Stock No. 21084-01 2/98
9-88
Advanced Information
CAT93CXXXX
RESET CIRCUIT CHARACTERISTICS
Symbol
t
GLITCH
V
RT
V
OLRS
V
OHRS
Parameter
Glitch Reject Pulse Width
Reset Threshold Hystersis
Reset Output Low Voltage (I
OLRS
=1mA)
Reset Output High Voltage
Reset Threshold (Vcc=5V)
(93CXXXX-45)
Reset Threshold (Vcc=5V)
(93CXXXX-42)
Min.
Max.
100
Units
ns
mV
15
0.4
Vcc-0.75
4.50
4.25
3.00
2.85
2.55
130
4.75
4.50
V
V
V
3.15
3.00
2.70
270
5
1
ms
µs
V
V
TH
Reset Threshold (Vcc=3.3V)
(93CXXXX-30)
Reset Threshold (Vcc=3.3V)
(93CXXXX-28)
Reset Threshold (Vcc=3V)
(93CXXXX-25)
t
PURST
t
RPD
Power-Up Reset Timeout
V
TH
to RESET Output Delay
RESET Output Valid
V
RVALID
Figure 1. RESET Output Timing
t
GLITCH
V
TH
V
RVALID
V
CC
t
PURST
t
RPD
t
PURST
RESET
t
RPD
RESET
9-89
Stock No. 21084-01 2/98
FPGA/CPLD
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