Preliminary W78C33B
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78C33B microcontroller supplies a wider frequency range than most 8-bit microcontrollers on
the market. It is functional compatible with the industry standard 80C32 microcontroller series except
the one extra 4-bit bit-addressable I/O port (Port 4).
The W78C33B contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters, and a serial
port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256
bytes of RAM, and the device supports ROMless operation for application programs.
The W78C33B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
•
8-bit CMOS microcontroller
•
Fully static design
•
Low standby current at full supply voltage
•
DC-40 MHz operation
•
256 bytes of on-chip scratchpad RAM
•
ROMless operation
•
64K bytes program memory address space
•
64K bytes data memory address space
•
Four 8-bit bidirectional ports
•
One extra
4-bit bidirectional port
•
Three 16-bit timer/counters
•
One full duplex serial port
•
Boolean processor
•
Six-
source, two-level interrupt capability
•
Built-in power management
•
Packages:
−
PLCC 44: W78C33BP-24/40
−
QFP 44: W78C33BF-24/40
−
TQFP 44: W78C33BM-24/40
-1-
Publication Release Date: June 1998
Revision A1
Preliminary W78C33B
PIN CONFIGURATIONS
44-Pin PLCC (W78C33BP)
T
2
E
X
,
P P P P
1 1 1 1
. . . .
4 3 2 1
A
D
0
,
P
P
4 V 0
. C .
2 C 0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
T
2
,
P
1
.
0
P1.5
P1.6
P1.7
RST
RXD, P3.0
P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
6 5 4 3 2 1 44 43 42 41 40
39
38
37
36
10
7
8
9
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X V P P
T S 4 2
A S . .
L
0 0
1
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
35
34
33
32
31
30
29
28
P
2
.
4
,
A
1
2
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
44-Pin QFP/TQFP (W78C33BF/W78C33BM)
T
2
E
X
,
P P P P
1 1 1 1
. . . .
4 3 2 1
T
2
,
P
1
.
0
A
D
0
,
P
P
4 V 0
. C .
2 C 0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
P1.5
P1.6
P1.7
RST
RXD, P3.0
P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
1
2
3
4
5
6
27
7
26
8
25
9
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
P
3
.
6
,
/
W
R
P
3
.
7
,
/
R
D
X
T
A
L
2
X V P P
T S 4 2
A S . .
L
0 0
1
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
-2-
Preliminary W78C33B
PIN DESCRIPTION
P0.0−P0.7
Port 0, Bits 0 through 7. Port 0 is a bi-directional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.
P1.0−P1.7
Port 1, Bits 0 through 7. Port 1 is a bi-directional I/O port with internal pull-ups. Pins P1.0 and P1.1
also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0−P2.7
Port 2, Bits 0 through 7. Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0−P3.7
Port 3, Bits 0 through 7. Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
PIN
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
ALTERNATE FUNCTION
RXD Serial Receive Data
TXD Serial Transmit Data
INT0 External Interrupt 0
INT1 External Interrupt 1
T0 Timer 0 Input
T1 Timer 1 Input
WR Data Write Strobe
RD Data Read Strobe
P4.0−P4.3
Port 4, Bits 0 through 3. Port 4 is a bi-directional I/O port with internal pull-ups.
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM.
This pin should be kept low for all W78C33B operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.
-3-
Publication Release Date: June 1998
Revision A1
Preliminary W78C33B
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high state during reset with a weak
pull-up.
PSEN
Program Store Enable Output, active low.
PSEN
enables the external ROM onto the Port 0
address/data bus during fetch and MOVC operations.
PSEN
goes to a high state during reset with a
weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
V
SS
, V
CC
Power Supplies. These are the chip ground and positive supplies.
BLOCK DIAGRAM
P1.0
~
P1.7
Port
1
Port 1
Latch
ACC
Interrupt
T1
Timer
2
Timer
0
Timer
1
UART
PSW
ALU
Stack
Pointer
T2
B
Port 0
Latch
Port
0
P0.0
~
P0.7
DPTR
Temp Reg.
PC
Incrementor
Addr. Reg.
P3.0
~
P3.7
Port
3
Port 3
Latch
Instruction
Decoder
&
Sequencer
SFR RAM
Address
256 bytes
RAM & SFR
Port
2
Bus & Clock
Controller
Port 2
Latch
P2.0
~
P2.7
P4.0
~
P4.3
Port
4
Port 4
Latch
Oscillator
Reset Block
Power control
XTAL1
XTAL2 ALE PSEN
RST
VCC
GND
-4-
Preliminary W78C33B
FUNCTIONAL DESCRIPTION
The W78C33B architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different instruction and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature
of the W78C33B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
Clock
The W78C33B is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C33B relatively insensitive to duty
cycle variations in the clock.
Crystal Oscillator
The W78C33B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.
-5-
Publication Release Date: June 1998
Revision A1
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