MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC12430/D
Rev. 5, 09/2001
High Frequency Clock
Synthesizer
The MC12430 is a general purpose synthesized clock source. Its
internal VCO will operate over a range of frequencies from 400 to 800
MHz. The differential PECL output can be configured to be the VCO
frequency divided by 1, 2, 4 or 8. With the output configured to divide the
VCO frequency by 2, and with a 16.000 MHz external quartz crystal used
to provide the reference frequency, the output frequency can be specified
in 1 MHz steps. The PLL loop filter is fully integrated so that no external
components are required. The synthesizer output frequency is configured
using a parallel or serial interface.
MC12430
See Upgrade Product – MPC9230
HIGH FREQUENCY PLL
CLOCK SYNTHESIZER
•
•
•
•
•
•
•
•
•
•
50 to 800 MHz Differential PECL Outputs
±25
ps Peak–to–Peak Output Jitter
Fully Integrated Phase–Locked Loop
Minimal Frequency Over–Shoot
Synthesized Architecture
Serial 3–Wire Interface
Parallel Interface for Power–Up
Quartz Crystal Interface
28–Lead PLCC and 32–Lead LQFP Packages
Operates from 3.3 V or 5.0V Power Supply
FA SUFFIX
FN SUFFIX
28–LEAD PLCC PACKAGE
CASE 776
4
Functional Description
32–LEAD LQFP PACKAGE
CASE 873A
The internal oscillator uses the external quartz crystal as the basis of its
frequency reference. The output of the reference oscillator is divided by
16 before being sent to the phase detector. With a 16 MHz crystal, this
provides a reference frequency of 1 MHz. Although this data sheet
illustrates functionality only for a 16 MHz crystal, any crystal in the 10–20
MHz range can be used.
The VCO within the PLL operates over a range of 400 to 800 MHz. Its output is scaled by a divider that is configured by either
the serial or parallel interfaces. The output of this loop divider is applied to the phase detector.
The phase detector and loop filter attempt to force the VCO output frequency to be M x 2 times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.
The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider
(N divider) is configured through either the serial or the parallel interfaces and can provide one of four division ratios (1, 2, 4 or 8).
This divider extends performance of the part while providing a 50% duty cycle.
The output driver is driven differentially from the output divider and is capable of driving a pair of transmission lines terminated
in 50Ω to V
CC
– 2.0 V. The positive reference for the output driver and the internal logic is separated from the power supply for the
phase–locked loop to minimize noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power
becomes valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority
over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the
application of the chip.
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the
programming section for more information.
The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the
programming section for more information.
Rev 5
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
379
MC12430
V
CC
25
S_CLOCK
S_DATA
S_LOAD
PLL-V
CC
FREF_EXT
XTAL_SEL
XTAL1
26
27
28
1
2
3
4
5
XTAL2
6
7
8
9
M[1]
10
M[2]
11
M[3]
FOUT
24
FOUT GND
23
22
V
CC
21
TEST GND
20
19
18
17
16
N[1]
N[0]
M[8]
M[7]
M[6]
Input
13
12
M[5]
M[4]
XTAL_SEL
OE
0
FREF_EXT
Disabled
1
XTAL
Enabled
N[1:0]
00
01
10
11
Output Division
2
4
8
1
28–Lead PLCC
15
14
OE P_LOAD M[0]
4
Figure 1. 28–Lead Pinout
(Top View)
V
CC
S_CLOCK
S_DATA
S_LOAD
PLL-V
CC
PLL-Vcc
FREF_EXT
XTAL_SEL
XTAL1
1
2
3
4
32
FOUT FOUT GND
31
30
29
V
CC
28
Vcc
27
TEST GND
26
25
24
23
22
21
N/C
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
32–Lead LQFP
5
6
7
8
20
19
18
17
9
10
11
12
13
M[1]
14
M[2]
15
M[3]
16
XTAL2 OE P_LOAD M[0]
N/C
Figure 2. 32–Lead Pinout
(Top View)
380
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
MC12430
PIN DESCRIPTIONS
Pin Name
Inputs
XTAL1, XTAL2
S_LOAD
(Int. Pulldown)
These pins form an oscillator when connected to an external series–resonant crystal.
This pin loads the configuration latches with the contents of the shift registers. The latches will be transparent
when this signal is HIGH, thus the data must be stable on the HIGH–to–LOW transition of S_LOAD for proper
operation.
This pin acts as the data input to the serial configuration shift registers.
This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the rising edge.
This pin loads the configuration latches with the contents of the parallel inputs .The latches will be transparent
when this signal is LOW, thus the parallel data must be stable on the LOW–to–HIGH transition of P_LOAD for
proper operation. P_LOAD is state sensitive.
These pins are used to configure the PLL loop divider. They are sampled on the LOW–to–HIGH transition of
P_LOAD. M[8] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled on the LOW–to–HIGH transition
of P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse generation on the
F
OUT
output.
Function
S_DATA
S_CLOCK
P_LOAD
(Int. Pulldown)
(Int. Pulldown)
(Int. Pullup)
M[8:0]
N[1:0]
OE
Outputs
F
OUT
, F
OUT
TEST
Power
V
CC
PLL_V
CC
GND
Other
(Int. Pullup)
(Int. Pullup)
(Int. Pullup)
4
These differential positive–referenced ECL signals (PECL) are the output of the synthesizer.
The function of this output is determined by the serial configuration bits T[2:0]. The output is single–ended ECL.
This is the positive supply for the internal logic and the output buffer of the chip, and is connected to +3.3V or
5.0V (V
CC
= PLL_V
CC
). Current drain through V
CC
≈
85 mA.
This is the positive supply for the PLL, and should be as noise–free as possible for low–jitter operation. This
supply is connected to +3.3V or 5.0V (V
CC
= PLL_V
CC
). Current drain through PLL_V
CC
≈
15 mA.
These pins are the negative supply for the chip and are normally all connected to ground.
FREF_EXT (Int. Pulldown)
XTAL_SEL
(Int. Pullup)
LVCMOS/CMOS input which can be used as the PLL reference.
LVCMOS/CMOS input that selects between the crystal and the FREF_EXT source for the PLL reference signal.
A HIGH selects the crystal input.
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
381
MC12430
+3.3 or 5.0V
PLL_V
CC
PHASE
DETECTOR
VCO
XTAL1
OSC
5
OE
S_LOAD
P_LOAD
6
28
7
0
S_DATA
S_CLOCK
27
26
V
CC1
21
+3.3 or 5.0V
8:16
9
M[8:0]
17, 18
2
N[1:0]
22, 19
9-BIT SR
1
2-BIT SR
0
1
3-BIT SR
XTAL2
LATCH
LATCH
9-BIT DIV M
COUNTER
DIV 2
DIV N
(1, 2, 4, 8)
V
CCO
25
24
23
FOUT
FOUT
XTAL_SEL
FREF_EXT
3
2
4
DIV 16
1MHz
F
REF
+3.3 or 5.0V
16MHz
200-400
MHz
400-800
MHz
20
TEST
LATCH
4
Figure 3. MC12430 Block Diagram (28–Lead PLCC Pinout)
PROGRAMMING INTERFACE
Programming the device amounts to properly configuring
the internal dividers to produce the desired frequency at the
outputs. The output frequency can by represented by this for-
mula:
FOUT = (F
XTAL
÷
16) x M x 2
÷
N
(1)
Where F
XTAL
is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it is
possible to select values of M such that the PLL is unable to
achieve loop lock. To avoid this, always make sure that M is
selected to be 200
≤
M
≤
400 for any input reference.
Assuming that a 16 MHz reference frequency is used, the
above equation reduces to:
FOUT = 2 x M
÷
N
Substituting the four values for N (1, 2, 4, 8) yields:
Output Frequency Range
N
1
2
4
8
382
FOUT
2xM
M
M
÷
2
M
÷
4
OUTPUT FREQUENCY RANGE
400 – 800 MHZ
200 – 400 MHZ
100 – 200 MHZ
50 – 100 MHZ
From these ranges, the user will establish the value of N
required, then the value of M can be calculated based on the
appropriate equation above. For example, if an output frequen-
cy of 131 MHz was desired, the following steps would be taken
to identify the appropriate M and N values. 131MHz falls within
the frequency range set by an N value of 4 so N [1:0] = 01. For
N = 4, FOUT = M
÷
2 and M = 2 x FOUT. Therefore, M = 131 x 2
= 262, so M[8:0] = 100000110. Following this same procedure,
a user can generate any whole frequency desired between 50
and 800MHz. Note that for N > 2 fractional values of FOUT can
be realized. The size of the programmable frequency steps
(and thus the indicator of the fractional output frequencies
achievable) will be equal to FXTAL
÷
8
÷
N.
For input reference frequencies other than 16 MHz, the set
of appropriate equations can be deduced from equation 1. For
computer applications, another useful frequency base would
be 16.666 MHz. From this reference, one can generate a fami-
ly of output frequencies at multiples of the 33.333 MHz PCI
clock. As an example, to generate a 133.333 MHz clock from a
16.666 MHz reference, the following M and N values would be
used:
FOUT = 16.666
÷
16 x M x 2
÷
N = 1.04166 x M x 2
÷
N
Let N = 4, M = 133.3333
÷
1.04166 x 2 = 256
The value for M falls within the constraints set for PLL stability,
therefore, N[1:0] = 01 and M[8:0] = 10000000. If the value for M
fell outside of the valid range, a different N value would be
selected to try to move M in the appropriate direction.
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
MC12430
The M and N counters can be loaded either through a paral-
lel or serial interface. The parallel interface is controlled via the
P_LOAD signal such that a LOW to HIGH transition will latch
the information present on the M[8:0] and N[1:0] inputs into the
M and N counters. When the P_LOAD signal is LOW, the input
latches will be transparent and any changes on the M[8:0] and
N[1:0] inputs will affect the FOUT output pair. To use the serial
port, the S_CLOCK signal samples the information on the
S_DATA line and loads it into a 14 bit shift register. Note that
the P_LOAD signal must be HIGH for the serial load operation
to function. The Test register is loaded with the first three bits,
the N register with the next two and the M register with the final
eight bits of the data stream on the S_DATA input. For each
register, the most significant bit is loaded first (T2, N1 and M8).
A pulse on the S_LOAD pin after the shift register is fully
loaded will transfer the divide values into the counters. The
HIGH to LOW transition on the S_LOAD input will latch the
new divide values into the counters. Figure 4 illustrates the
timing diagram for both a parallel and a serial load of the
MC12430 synthesizer.
M[8:0] and N[1:0] are normally specified once at power–up
through the parallel interface, and then possibly again through
the serial interface. This approach allows the application to
come up at one frequency and then change or fine–tune the
clock as the ability to control the serial interface becomes
available.
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the parallel
interface. The T2, T1 and T0 control bits are preset to ‘000’
when P_LOAD is LOW so that the PECL FOUT outputs are as
jitter–free as possible. Any active signal on the TEST output
pin will have detrimental affects on the jitter of the PECL output
pair. In normal operations, jitter specifications are only guaran-
teed if the TEST output is static. The serial configuration port
can be used to select one of the alternate functions for this pin.
Most of the signals available on the TEST output pin are
useful only for performance verification of the MC12430 itself.
However, the PLL bypass mode may be of interest at the board
level for functional debug. When T[2:0] is set to 110 the
MC12430 is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers. The N
divider drives the FOUT differential pair and the M counter
drives the TEST output pin. In this mode the S_CLOCK input
could be used for low speed board level functional test or de-
bug. Bypassing the PLL and driving FOUT directly gives the
user more control on the test clocks sent through the clock
tree. Figure 5 shows the functional setup of the PLL bypass
mode. Because the S_CLOCK is a CMOS level, the input fre-
quency is limited to 250 MHz or less. This means the fastest
the FOUT pin can be toggled via the S_CLOCK is 250MHz as
the minimum divide ratio of the N counter is 1. Note that the M
counter output on the TEST output will not be a 50% duty cycle
due to the way the divider is implemented.
T2
0
0
0
0
1
1
1
1
T1
0
0
1
1
0
0
1
1
T0
0
1
0
1
0
1
0
1
TEST
(Pin 20)
SHIFT REGISTER OUT
HIGH
FREF
M COUNTER OUT/2
FOUT
LOW
M COUNTER/2 in
PLL Bypass Mode
FOUT/4
4
S_CLOCK
S_DATA
S_LOAD
M[8:0]
N[1:0]
P_LOAD
M, N
T2
First
Bit
T1
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
Last
Bit
Figure 4. Timing Diagram
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
383
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