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TMS320VC5502
Fixed-Point Digital Signal Processor
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS166K
April 2001 – Revised November 2008
TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166K – APRIL 2001 – REVISED NOVEMBER 2008
www.ti.com
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data sheet revision history highlights the technical changes made to the SPRS166J device-specific
data sheet to make it an SPRS166K revision.
Scope:
See table below.
ADDITIONS/CHANGES/DELETIONS
Table 2-4,
Signal Descriptions:
•
HD[7:0]: removed "M" from "OTHER" column
•
HC0: removed "M" from "OTHER" column
•
HC1: removed "M" from "OTHER" column
•
HCNTL0: removed "M" from "OTHER" column
•
HCNTL1: removed "M" from "OTHER" column
•
HCS: removed "M" from "OTHER" column
•
HR/W: removed "M" from "OTHER" column
Table 3-30,
Peripheral IDLE Control Register Bit Field Description:
•
Updated footnote
Figure 5-22,
Reset Timings:
•
Added footnote about the state of the DSP pins during power up
2
Revision History
Submit Documentation Feedback
TMS320VC5502
Fixed-Point Digital Signal Processor
www.ti.com
SPRS166K – APRIL 2001 – REVISED NOVEMBER 2008
Contents
Revision History
...........................................................................................................................
2
1
TMS320VC5502
.................................................................................................................
15
1.1
Features
.....................................................................................................................
15
Description
..................................................................................................................
Pin Assignments
............................................................................................................
2.2.1
Ball Grid Array (GZZ and ZZZ)
................................................................................
2.2.2
Low-Profile Quad Flatpack (PGF)
.............................................................................
2.2.3
Signal Descriptions
..............................................................................................
Memory
......................................................................................................................
3.1.1
On-Chip ROM
...................................................................................................
3.1.2
On-Chip Dual-Access RAM (DARAM)
........................................................................
3.1.3
Instruction Cache
................................................................................................
3.1.4
Memory Map
.....................................................................................................
3.1.5
Boot Configuration
...............................................................................................
Peripherals
..................................................................................................................
Configurable External Ports and Signals
................................................................................
3.3.1
Parallel Port Mux
................................................................................................
3.3.2
Host Port Mux
....................................................................................................
3.3.3
Serial Port 2 Mux
................................................................................................
3.3.4
External Bus Selection Register (XBSR)
.....................................................................
Configuration Examples
...................................................................................................
Timers
........................................................................................................................
3.5.1
Timer Interrupts
..................................................................................................
3.5.2
Timer Pins
........................................................................................................
3.5.3
Timer Signal Selection Register (TSSR)
.....................................................................
Universal Asynchronous Receiver/Transmitter (UART)
...............................................................
Inter-Integrated Circuit (I
2
C) Module
.....................................................................................
Host-Port Interface (HPI)
..................................................................................................
Direct Memory Access (DMA) Controller
................................................................................
3.9.1
DMA Channel 0 Control Register (DMA_CCR0)
...........................................................
System Clock Generator
..................................................................................................
3.10.1 Input Clock Source
..............................................................................................
3.10.1.1 Internal System Oscillator With External Crystal
................................................
3.10.1.2 Clock Generation With PLL Disabled (Bypass Mode, Default)
................................
3.10.1.3 Clock Generation With PLL Enabled (PLL Mode)
..............................................
3.10.1.4 Frequency Ranges for Internal Clocks
...........................................................
3.10.2 Clock Groups
.....................................................................................................
3.10.2.1 C55x Subsystem Clock Group
....................................................................
3.10.2.2 Fast Peripherals Clock Group
.....................................................................
3.10.2.3 Slow Peripherals Clock Group
....................................................................
3.10.2.4 External Memory Interface Clock Group
.........................................................
3.10.3 EMIF Input Clock Selection
....................................................................................
3.10.4 Changing the Clock Group Frequencies
.....................................................................
3.10.4.1 C55x Subsystem Clock Group
....................................................................
3.10.4.2 Fast Peripherals Clock Group
.....................................................................
3.10.4.3 Slow Peripherals Clock Group
....................................................................
3.10.4.4 External Memory Interface Clock Group
.........................................................
3.10.5 PLL Control Registers
..........................................................................................
Contents
2
Introduction
.......................................................................................................................
16
2.1
2.2
16
17
17
19
21
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3
3
Functional Overview
...........................................................................................................
33
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166K – APRIL 2001 – REVISED NOVEMBER 2008
www.ti.com
3.11
3.12
3.10.5.1 PLL Control / Status Register (PLLCSR)
........................................................
3.10.5.2 PLL Multiplier Control Register (PLLM)
..........................................................
3.10.5.3 PLL Divider 0 Register (PLLDIV0) (Prescaler)
..................................................
3.10.5.4 PLL Divider1 Register (PLLDIV1) for SYSCLK1
................................................
3.10.5.5 PLL Divider2 Register (PLLDIV2) for SYSCLK2
................................................
3.10.5.6 PLL Divider3 Register (PLLDIV3) for SYSCLK3
................................................
3.10.5.7 Oscillator Divider1 Register (OSCDIV1) for CLKOUT3
........................................
3.10.5.8 Oscillator Wakeup Control Register (WKEN)
....................................................
3.10.5.9 CLKOUT3 Select Register (CK3SEL)
............................................................
3.10.5.10 CLKOUT Selection Register (CLKOUTSR)
....................................................
3.10.5.11 Clock Mode Control Register (CLKMD)
........................................................
3.10.6 Reset Sequence
.................................................................................................
Idle Control
..................................................................................................................
3.11.1 Clock Domains
...................................................................................................
3.11.2 IDLE Procedures
................................................................................................
3.11.2.1 CPU Domain Idle Procedure
......................................................................
3.11.2.2 Master Port Domain (DMA/HPI) Idle Procedure
................................................
3.11.2.3 Peripheral Modules Idle Procedure
...............................................................
3.11.2.4 EMIF Module Idle Procedure
......................................................................
3.11.2.5 IDLE2 Mode
..........................................................................................
3.11.2.6 IDLE3 Mode
..........................................................................................
3.11.2.7 IDLE3 Mode With Internal Oscillator Disabled
..................................................
3.11.3 Module Behavior at Entering IDLE State
.....................................................................
3.11.4 Wake-Up Procedure
............................................................................................
3.11.4.1 CPU Domain Wake-up Procedure
................................................................
3.11.4.2 Master Port Domain (DMA/HPI) Wake-up Procedure
..........................................
3.11.4.3 Peripheral Modules Wake-up Procedure
........................................................
3.11.4.4 EMIF Module Wake-up Procedure
................................................................
3.11.4.5 IDLE2 Mode Wake-up Procedure
.................................................................
3.11.4.6 IDLE3 Mode Wake-up Procedure
.................................................................
3.11.4.7 IDLE3 Mode With Internal Oscillator Disabled Wake-up Procedure
.........................
3.11.4.8 Summary of Wake-up Procedures
................................................................
3.11.5 Auto-Wakeup/Idle Function for McBSP and DMA
...........................................................
3.11.6 Clock State of Multiplexed Modules
...........................................................................
3.11.7 IDLE Control and Status Registers
............................................................................
3.11.7.1 IDLE Configuration Register (ICR)
................................................................
3.11.7.2 IDLE Status Register (ISTR)
.......................................................................
3.11.7.3 Peripheral IDLE Control Register (PICR)
........................................................
3.11.7.4 Peripheral IDLE Status Register (PISTR)
........................................................
3.11.7.5 Master IDLE Control Register (MICR)
............................................................
3.11.7.6 Master IDLE Status Register (MISR)
.............................................................
General-Purpose I/O (GPIO)
.............................................................................................
3.12.1 General-Purpose I/O Port
......................................................................................
3.12.1.1 General-Purpose I/O Direction Register (IODIR)
...............................................
3.12.1.2 General-Purpose I/O Data Register (IODATA)
..................................................
3.12.2 Parallel Port General-Purpose I/O (PGPIO)
.................................................................
3.12.2.1 Parallel GPIO Enable Register 0 (PGPIOEN0)
.................................................
3.12.2.2 Parallel GPIO Direction Register 0 (PGPIODIR0)
..............................................
3.12.2.3 Parallel GPIO Data Register 0 (PGPIODAT0)
..................................................
3.12.2.4 Parallel GPIO Enable Register 1 (PGPIOEN1)
.................................................
3.12.2.5 Parallel GPIO Direction Register 1 (PGPIODIR1)
..............................................
3.12.2.6 Parallel GPIO Data Register 1 (PGPIODAT1)
..................................................
3.12.2.7 Parallel GPIO Enable Register 2 (PGPIOEN2)
.................................................
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Contents
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