ICS950602YGLFT datasheet, PDF - EEWORLD Datasheet

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ICS950602YGLFT: DescriptionProcessor Specific Clock Generator, 200MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48; CategoryThe embedded processor and controller Microcontrollers and processors; File Size145KB，16 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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ICS950602YGLFT Overview

Processor Specific Clock Generator, 200MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48

ICS950602YGLFT Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
Contacts	48
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	R-PDSO-G48
JESD-609 code	e3
length	12.5 mm
Number of terminals	48
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	200 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	14.32 MHz
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	6.1 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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Integrated

Circuit

Systems, Inc.

ICS950602

Programmable Timing Control Hub™ for PII/III™

Recommended Application:

VIA Mobile PL133T and PLE133T Chipsets.

Output Features:

•

2 - CPU clocks @ 2.5V

•

1 - Pairs of differential CPU clocks @ 3.3V

•

7 - PCI including 1 free running @ 3.3V

•

7 - SDRAM @ 3.3V

•

1 - 48MHz @ 3.3V fixed

•

1 - 24_48MHz selectable @ 3.3V

•

2 - REF @ 3.3V, 14.318MHz

Features/Benefits:

•

Programmable output frequency.

•

Programmable output divider ratios.

•

Programmable output rise/fall time.

•

Programmable output skew.

•

Programmable spread percentage for EMI control.

•

Watchdog timer technology to reset system

if system malfunctions.

•

Programmable watch dog safe frequency.

•

Support I

C Index read/write and block read/write

operations.

•

Uses external 14.318MHz crystal.

Key Specifications:

•

CPU Output Jitter <200ps

•

CPU Output Skew <175ps

•

PCI to PCI Output Skew <500ps

GND

*FS2/REF1

REF0

Vtt_PWRGD#

VDDREF

GND

VDDPCI

*FS4/PCICLK_F

*FS3/PCICLK0

GND

PCICLK1

PCICLK2

PCICLK3

PCICLK4

PCICLK5

SDRAM_IN

*CPU_STOP#

*PCI_STOP#

*PD#

**MULTISEL

GND

SDATA

Pin Configuration

CPUCLK0

CPUCLK1

VDDCPU_2.5

VDDCPU_3.3

CPUCLKT

CPUCLKC

GND

RESET#

I REF

SDRAM6

GND

SDRAM0

SDRAM1

VDDSDRAM

SDRAM2

SDRAM3

GND

SDRAM4

SDRAM5

VDDSDRAM

AVDD48

48MHz/FS0*

24_48MHz/FS1*

SCLK

48-Pin SSOP & TSSOP

* Internal Pull-up resistor of 120K to VDD

** these inputs have 120K internal pull-down

to GND

Block Diagram

Host Swing Select Functions

MULTISEL0

Board Target

Trace/Term Z

50 ohms

Reference R,

Iref = V

/(3*Rr)

Rr = 221 1%,

Iref = 5.00mA

Rr = 475 1%,

Iref = 2.32mA

Output

Current

Ioh = 4* I REF

Ioh = 6* I REF

Voh @ Z

1.0V @ 50

0.7V @ 50

0469B—12/18/02

ICS950602

ICS950602YGLFT Related Products

	ICS950602YGLFT	ICS950602YFLFT	ICS950602YGT
Description	Processor Specific Clock Generator, 200MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48	Processor Specific Clock Generator, 200MHz, PDSO48, 0.300 INCH, MO-118, SSOP-48	Processor Specific Clock Generator, 200MHz, PDSO48, 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48
Is it lead-free?	Lead free	Lead free	Contains lead
Is it Rohs certified?	conform to	conform to	incompatible
Parts packaging code	TSSOP	SSOP	TSSOP
package instruction	6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48	0.300 INCH, MO-118, SSOP-48	TSSOP,
Contacts	48	48	48
Reach Compliance Code	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99
JESD-30 code	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48
JESD-609 code	e3	e3	e0
length	12.5 mm	15.875 mm	12.5 mm
Number of terminals	48	48	48
Maximum operating temperature	70 °C	70 °C	70 °C
Maximum output clock frequency	200 MHz	200 MHz	200 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	260	240
Master clock/crystal nominal frequency	14.32 MHz	14.32 MHz	14.32 MHz
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	2.8 mm	1.2 mm
Maximum supply voltage	3.465 V	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)	TIN LEAD
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.635 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	20
width	6.1 mm	7.5 mm	6.1 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	-
Base Number Matches	-	1	1

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