Integrated
Circuit
Systems, Inc.
ICS950602
Programmable Timing Control Hub™ for PII/III™
Recommended Application:
VIA Mobile PL133T and PLE133T Chipsets.
Output Features:
•
2 - CPU clocks @ 2.5V
•
1 - Pairs of differential CPU clocks @ 3.3V
•
7 - PCI including 1 free running @ 3.3V
•
7 - SDRAM @ 3.3V
•
1 - 48MHz @ 3.3V fixed
•
1 - 24_48MHz selectable @ 3.3V
•
2 - REF @ 3.3V, 14.318MHz
Features/Benefits:
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I
2
C Index read/write and block read/write
operations.
•
Uses external 14.318MHz crystal.
Key Specifications:
•
CPU Output Jitter <200ps
•
CPU Output Skew <175ps
•
PCI to PCI Output Skew <500ps
GND
*FS2/REF1
REF0
Vtt_PWRGD#
VDDREF
GND
X1
X2
VDDPCI
*FS4/PCICLK_F
*FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
SDRAM_IN
*CPU_STOP#
*PCI_STOP#
*PD#
**MULTISEL
GND
SDATA
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CPUCLK0
CPUCLK1
VDDCPU_2.5
VDDCPU_3.3
CPUCLKT
CPUCLKC
GND
RESET#
I REF
SDRAM6
GND
SDRAM0
SDRAM1
VDDSDRAM
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDRAM
AVDD48
48MHz/FS0*
24_48MHz/FS1*
SCLK
48-Pin SSOP & TSSOP
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
Block Diagram
Host Swing Select Functions
MULTISEL0
0
1
Board Target
Trace/Term Z
50 ohms
50 ohms
Reference R,
Iref = V
DD
/(3*Rr)
Rr = 221 1%,
Iref = 5.00mA
Rr = 475 1%,
Iref = 2.32mA
Output
Current
Ioh = 4* I REF
Ioh = 6* I REF
Voh @ Z
1.0V @ 50
0.7V @ 50
0469B—12/18/02
ICS950602
Integrated
Circuit
Systems, Inc.
ICS950602
General Description
The
ICS950602
is a single chip clock solution for VIA Mobile PL133T and PLE133T chipsets. It provides all necessary clock
signals for such a system.
The
ICS950602
is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With
all these programmable features, ICS' TCH makes motherboard testing, tuning and improvement very simple.
Pin Description
PIN NUMBER
1, 6, 12, 23,
32, 38, 42,
5, 9, 29, 35
2
3
4
7
8
10
PCICLK_F
11
17, 16, 15, 14, 13
18
19
20
21
22
24
25
26
FS3
PCICLK0
PCICLK (5:1)
SDRAM_IN
CPU_STOP#
PCI_STOP#
PD#
MULTSEL
SDATA
SCLK
FS1
48_24MHz
FS0
27
48MHz
28
30, 31, 33, 34, 36,
37, 39
40
41
43
44
45
46
47, 48
0469B—12/18/02
PIN NAME
GND
VDD
FS2
REF1
REF0
Vtt_PWRGD#
X1
X2
FS4
TYPE
PWR
PWR
IN
OUT
OUT
IN
IN
OUT
IN
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
I/O
IN
IN
OUT
IN
OUT
PWR
OUT
OUT
OUT
OUT
OUT
PWR
PWR
OUT
Ground pins for 3.3V supply
3 . 3 V p ow e r s u p p l y
DESCRIPTION
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V, 14.318MHz reference clock output.
3.3V, 14.318MHz reference clock output.
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0)
are valid and are ready to be sampled (active low)
Cr ystal input, has inter nal load cap (33pF) and feedback resistor from X2
Cr ystal output, nominally 14.318MHz. Has inter nal load cap (33pF)
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V PCI clock output
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V PCI clock output
3.3V PCI clock outputs
SDRAM buffer input pin.
Stops all CPUCLKs clocks at logic 0 level, when input low
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
w h e n i n p u t l ow
Asynchronous active low input pin used to power down the device into a low
power state. The inter nal clocks are disabled and the VCO and the cr ystal are
s t o p p e d . T h e l a t e n c y o f t h e p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 3 m s.
3.3V LVTTL input for selecting the current multiplier for CPU outputs.
Data pin for I
2
C circuitry 5V tolerant
Clock pin for I
2
C circuitry 5V tolerant
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
Selectable 48 or 24MHz output
L o g i c i n p u t f r e q u e n c y s e l e c t b i t . I n p u t l a t c h e d a t p ow e r o n .
3.3V Fixed 48MHz clock output.
3.3V analog power supply for 48 or 24MHz outputs.
SDRAM clock outputs.
This pin establishes the reference current for the CPUCLK pairs. This pin requires
a fixed precision resistor tied to ground in order to establish the appropriate
current.
Real time system reset signal for frequency value or watchdog timer timeout. This
signal is active low.
"Complementary" clock of differential pair CPU outputs. These are current outputs
and external resistors are required for voltage bias.
"True" clock of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
3.3V power for CPU differential clocks.
2.5V power for CPU clocks.
CPU clock outputs.
AVDD48
SDRAM (5:0, 6)
I REF
RESET#
CPUCLKC
CPUCLKT
VDDCPU_3.3
VDDCPU_2.5
CPUCLK (1:0)
2
Integrated
Circuit
Systems, Inc.
ICS950602
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D3
(H)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
*See notes on the following page
.
0469B—12/18/02
3
Integrated
Circuit
Systems, Inc.
ICS950602
Byte 0: Functionality and frequency select register (Default=0)
Bit
Description
Bit2 Bit1 Bit6 Bit5 Bit4 CPUCLK PCICLK
MHz
MHz
FS4 FS3 FS2 FS1 FS0
Spread %
PWD
Bit
(2:1,6:4)
Bit 3
Bit 0
Bit 7
0
0
0
0
0
200.00
33.30
+/-0.25% center spread
0
0
0
0
1
190.00
38.00
+/-0.25% center spread
0
0
0
1
0
180.00
36.00
+/-0.25% center spread
0
0
0
1
1
170.00
34.00
+/-0.25% center spread
0
0
1
0
0
166.00
33.20
+/-0.25% center spread
0
0
1
0
1
160.00
32.00
+/-0.25% center spread
0
0
1
1
0
150.00
37.50
+/-0.25% center spread
0
0
1
1
1
145.00
36.30
+/-0.25% center spread
0
1
0
0
0
140.00
35.00
+/-0.25% center spread
0
1
0
0
1
136.00
34.00
+/-0.25% center spread
0
1
0
1
0
130.00
32.50
+/-0.25% center spread
0
1
0
1
1
124.00
31.00
+/-0.25% center spread
0
1
1
0
0
67.20
33.60
+/-0.25% center spread
0
1
1
0
1
100.90
33.63
+/-0.25% center spread
0
1
1
1
0
118.00
39.30
+/-0.25% center spread
0
1
1
1
1
134.40
33.60
+/-0.25% center spread
1
0
0
0
0
67.00
33.50
+/-0.25% center spread
1
0
0
0
1
100.50
33.50
+/-0.25% center spread
1
0
0
1
0
115.00
38.30
+/-0.25% center spread
1
0
0
1
1
133.90
33.47
+/-0.25% center spread
1
0
1
0
0
66.80
33.40
+/-0.25% center spread
1
0
1
0
1
100.20
33.40
+/-0.25% center spread
1
0
1
1
0
110.00
36.70
+/-0.25% center spread
1
0
1
1
1
133.60
33.40
+/-0.25% center spread
1
1
0
0
0
105.00
35.00
+/-0.25% center spread
1
1
0
0
1
90.00
30.00
+/-0.25% center spread
1
1
0
1
0
85.00
28.30
+/-0.25% center spread
1
1
0
1
1
78.00
39.00
+/-0.25% center spread
1
1
1
0
0
66.60
33.30
+/-0.25% center spread
1
1
1
0
1
100.00
33.30
0 to -0.5% down spread
1
1
1
1
0
75.00
37.50
+/-0.25% center spread
1
1
1
1
1
133.30
33.30
0 to -0.5% down spread
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2,7:4
0 - Normal
1 - Spread spectrum enable
0 - Watch dog safe frequency will be selected by latch inputs
1 - Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Note 1
0
0
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0469B—12/18/02
4
Integrated
Circuit
Systems, Inc.
ICS950602
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
-
-
-
-
-
48
47
44, 43
PWD
X
X
X
X
X
1
1
1
Description
FS4 Read back
FS3 Read back
FS2 Read back
FS1 Read back
FS0 Read back
CPUCLK0
CPUCLK1
CPUCLKT, CPUCLKC
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
39
10
17
16
15
14
13
11
PWD
1
1
1
1
1
1
1
1
Description
SDRAM6
PCICLK_F
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
-
-
27
26
-
31, 30
34, 33
37, 36
PWD
0
0
1
1
0
1
1
1
Description
RESET gear shift detect 1 = Enable, 0 = Disable
S E L24_48: 0 = 24, 1 = 48
48MHz
24_48MHz
Reserved
SDRAM (4:5)
SDRAM (2:3)
SDRAM (0:1)
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Pin#
-
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
X
Description
MULTSEL Read back
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0469B—12/18/02
5
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