LS352
MONOLITHIC DUAL
PNP TRANSISTOR
Linear Systems Monolithic Dual PNP Transistor
The LS352 is a monolithic pair of PNP transistors
mounted in a single P-DIP package. The monolithic
dual chip design reduces parasitics and gives better
performance while ensuring extremely tight matching.
The 8 Pin P-DIP provides ease of manufacturing, and
the symmetrical pinout prevents improper orientation.
(See Packaging Information).
LS352 Features:
Very high gain
Tight matching
Low Output Capacitance
FEATURES
HIGH GAIN
TIGHT V
BE
MATCHING
HIGH f
t
ABSOLUTE MAXIMUM RATINGS
1
@ 25°C (unless otherwise noted)
Maximum Temperatures
Storage Temperature
Operating Junction Temperature
Maximum Power Dissipation
Continuous Power Dissipation (One side)
Continuous Power Dissipation (Both sides)
Linear Derating factor (One side)
Linear Derating factor (Both sides)
Maximum Currents
Collector Current
MIN
‐‐
‐‐
‐‐
‐‐
‐‐
TYP
0.2
0.5
‐‐
‐‐
5
MAX
0.5
2
5
0.3
‐‐
UNITS
mV
µV/°C
nA
nA/°C
%
h
FE
≥ 200 @ 10µA‐1mA
|V
BE1
– V
BE2
|= 0.2mV TYP.
275MHz TYP. @ 1mA
‐65°C to +200°C
‐55°C to +150°C
250mW
500mW
2.3mW/°C
4.3mW/°C
10mA
CONDITIONS
I
C
= 10µA, V
CE
= 5V
I
C
= 10µA, V
CE
= 5V
T
A
= ‐55°C to +125°C
I
C
= 10µA, V
CE
= 5V
I
C
= 10µA, V
CE
= 5V
T
A
= ‐55°C to +125°C
I
C
= 10µA, V
CE
= 5V
MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated)
SYMBOL
CHARACTERISTIC
|V
BE1
– V
BE2
|
Base Emitter Voltage Differential
∆|(V
BE1
– V
BE2
)| / ∆T
Base Emitter Voltage Differential
Change with Temperature
|I
B1
– I
B2
|
Base Current Differential
|∆ (I
B1
– I
B2
)|/°C
Base Current Differential
Change with Temperature
h
FE1
/h
FE2
DC Current Gain Differential
ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted)
SYMBOL
CHARACTERISTICS
MIN.
BV
CBO
Collector to Base Voltage
60
BV
CEO
Collector to Emitter Voltage
60
BV
EBO
Emitter‐Base Breakdown Voltage
6.2
BV
CCO
Collector to Collector Voltage
100
200
DC Current Gain
h
FE
200
200
V
CE
(SAT)
Collector Saturation Voltage
‐‐
I
EBO
Emitter Cutoff Current
‐‐
I
CBO
Collector Cutoff Current
‐‐
C
OBO
Output Capacitance
‐‐
C
C1C2
Collector to Collector Capacitance
‐‐
I
C1C2
Collector to Collector Leakage Current
‐‐
f
T
Current Gain Bandwidth Product
200
NF
Narrow Band Noise Figure
‐‐
Click To Buy
TYP.
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
‐‐
MAX.
‐‐
‐‐
‐‐
‐‐
600
600
‐‐
0.5
0.2
0.2
2
2
0.5
‐‐
3
UNITS
V
V
V
V
V
nA
nA
pF
pF
nA
MHz
dB
CONDITIONS
I
C
= 10µA, I
E
= 0
I
C
= 10µA, I
B
= 0
I
E
= 10µA, I
C
= 0
2
I
C
= 10µA, I
E
= 0
I
C
= 10µA, V
CE
= 5V
I
C
= 100µA, V
CE
= 5V
I
C
= 1mA, V
CE
= 5V
I
C
= 1mA, I
B
= 0.1mA
I
E
= 0, V
CB
= 3V
I
E
= 0, V
CB
= 20V
I
E
= 0, V
CB
= 5V
V
CC
= 0V
V
CC
= ±45V
I
C
= 1mA, V
CE
= 5V
I
C
= 100µA, V
CE
= 5V, BW=200Hz, R
G
= 10KΩ,
f = 1KHz
Notes:
1. Absolute Maximum ratings are limiting values above which serviceability may be impaired
2. The reverse base‐to‐emitter voltage must never exceed 6.2 volts; the reverse base‐to‐emitter current must never exceed 10µA.
P-DIP (Top View)
Available Packages:
LS352 in P-DIP
LS352 available as bare die
Please contact Micross for full package and die dimensions:
Email:
chipcomponents@micross.com
Web:
www.micross.com/distribution.aspx
Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or
other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.
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