AS29LV400B-70BCC datasheet, PDF

Datasheet> All Categories > storage> storage> AS29LV400B-70BCC

AS29LV400B-70BCC: DescriptionFlash, 256KX16, 70ns, PBGA48, 6 X 8 MM, 1.20 MM HEIGHT, BGA-48; Categorystorage storage; File Size311KB，21 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

Download Datasheet Parametric View All

AS29LV400B-70BCC Overview

Flash, 256KX16, 70ns, PBGA48, 6 X 8 MM, 1.20 MM HEIGHT, BGA-48

AS29LV400B-70BCC Parametric

Parameter Name	Attribute value
Maker	ALSC [Alliance Semiconductor Corporation]
Parts packaging code	BGA
package instruction	6 X 8 MM, 1.20 MM HEIGHT, BGA-48
Contacts	48
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	70 ns
Spare memory width	8
startup block	BOTTOM
JESD-30 code	R-PBGA-B48
length	8 mm
memory density	4194304 bit
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of terminals	48
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Programming voltage	3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
type	NOR TYPE
width	6 mm

AS29LV400B-70BCC Preview

Preliminary Information

July 2001

AS29LV400

3V 512K x 8/256K × 16 CMOS Flash EEPROM

Features

• Organization: 512Kx8/256Kx16

• Sector architecture

- One 16K; two 8K; one 32K; and seven 64K byte sectors

- One 8K; two 4K; one 16K; and seven 32K word sectors

- Boot code sector architecture—T (top) or B (bottom)

- Erase any combination of sectors or full chip

• Single 2.7-3.6V power supply for read/write operations

• Sector protection

• High speed 70/80/90/120 ns address access time

• Automated on-chip programming algorithm

- Automatically programs/verifies data at specified address

• Automated on-chip erase algorithm

- Automatically preprograms/erases chip or specified

sectors

• Hardware

RES ET

- Resets internal state machine to read mode

• Low power consumption

- 200 nA typical automatic sleep mode current

- 200 nA typical standby current

- 10 mA typical read current

• JEDEC standard software, packages and pinouts

- 48-pin TSOP

- 44-pin SO; availability TBD

- 48-pin BGA

• Detection of program/erase cycle completion

- DQ7

DATA

polling

- DQ6 toggle bit

- DQ2 toggle bit

- RY/

B Y

output

• Erase suspend/resume

- Supports reading data from or programming data

to a sector not being erased

• Low V

write lock-out below 1.5V

• 10 year data retention at 150C

• 100,000 write/erase cycle endurance

Logic block diagram

RY/

Sector protect/

erase voltage

switches

Erase voltage

generator

DQ0–DQ15

RESE T

B Y TE

A-1

Program/erase

control

Command

Input/output

buffers

Program voltage

generator

Chip enable

Output enable

Logic

STB

Data latch

detector

Timer

Address latch

STB

Y decoder

Y gating

X decoder

Cell matrix

A0–A17

Selection guide

29LV400-70

Maximum access time

Maximum chip enable access time

Maximum output enable access time

29LV400-80

29LV400-90

29LV400-120

120

Unit

7/13/01; V.0.9.8

Alliance Semiconductor

P. 1 of 21

AS29LV400

Pin arrangements

RESET

RY/BY

A17

A15

A14

A13

A12

A11

A10

48-pin TSOP

AS29LV400

44-pin SO (availability TBD)

BY/RY

A17

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

AS29LV400

DQ0

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

RESET

A10

A11

A12

A13

A14

A15

A16

DQ15/A-1

BYTE

A16

BY T E

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

48-ball BGA Ball Assignment

7/13/01; V.0.9.8

Alliance Semiconductor

P. 2 of 21

AS29LV400

Functional description

The AS29LV400 is an 4 megabit, 3.0 volt Flash memory organized as 512Kbyte of 8 bits/256Kbytes of 16 bits each. For flexible

Erase and Program capability, the 4 megabits of data is divided into eleven sectors: one 16K, two 8K, one 32K, and seven 64k

byte sectors; or one 8K, two 4K, one 16K, and seven 32K word sectors. The ×8 data appears on DQ0–DQ7; the ×16 data appears

on DQ0–DQ15. The AS29LV400 is offered in JEDEC standard 48-pin TSOP, 44-pin SO and 48-pin BGA. This device is designed

to be programmed and erased with a single 3.0V V

supply. The device can also be reprogrammed in standard EPROM

programmers.

The AS29LV400 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To

eliminate bus contention the device has separate chip enable

(

)

, write enable

(

)

, and output enable

(

O E

)

controls. Word

mode (×16 output) is selected by B Y T E = high. Byte mode (×8 output) is selected by B Y T E = low.

The AS29LV400 is fully compatible with the JEDEC single power supply Flash standard. The device uses standard microprocessor

write timings to send Write commands to the register. An internal state-machine uses register contents to control the erase and

programming circuitry. Write cycles also internally latch addresses and data needed for the Programming and Erase operations.

Data is read in the same manner as other Flash or EPROM devices. Use the Program command sequence to invoke the on-chip

programming algorithm that automatically times the program pulse widths, and verifies proper cell margin. Use the Erase

command sequence to invoke the automated on-chip erase algorithm that preprograms the sector when it is not already

programmed before executing the erase operation. The Erase command also times the erase pulse widths and verifies the proper

cell margins.

Boot sector architecture enables the system to boot from either the top (AS29LV400T) or the bottom (AS29LV400B) sector.

Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other

sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both the Program and the

Erase operations in all, or any combination of the eleven sectors. The device provides true background erase with Erase Suspend,

which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The Chip

Erase command will automatically erase all unprotected sectors.

When shipped from the factory, AS29LV400 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is

programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change

bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no

effect on other sectors.

The device features a single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and regulated

voltages are provided for the Program and Erase operations. A low V

C C

detector automatically inhibits write operations during

power transtitions. The

RY/

B Y pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect the end of the program or

to erase operations. The device automatically resets to the Read mode after the Program or Erase operations are completed. DQ2

indicates which sectors are being erased.

The AS29LV400 resists accidental erasure or spurious programming signals resulting from power transitions. The Control

register architecture permits alteration of memory contents only when successful completion of specific command sequences has

occured. During power up, the device is set to Read mode with all Program/Erase commands disabled if V

is less than V

LKO

(lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE

CE,

W E. To initiate Write

commands, CE and W E must be a logical zero and O E a logical 1.

When the device’s hardware R ESE T pin is driven low, any Program/Erase operation in progress is terminated and the internal

state machine is reset to Read mode. If the R ESE T pin is tied to the system reset circuitry and a system reset occurs during an

automated on-chip Program/Erase algorithm, the operating data in the address locations may become corrupted and require

rewriting. Resetting the device enables the system’s microprocessor to read boot-up firmware from the Flash memory.

The AS29LV400 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are

programmed one at a time using the EPROM programming mechanism of hot electron injection.

7/13/01; V.0.9.8

Alliance Semiconductor

P. 3 of 21

AS29LV400

Operating modes

Mode

ID read MFR code

ID read device code

Read

Standby

Output disable

Write

Enable sector protect

Sector unprotect

Temporary sector

unprotect

Verify sector protect

†

Hardware Reset

Pulse/L

RE SET

Code

OUT

High Z

Code

High Z

Verify sector unprotect

†

L = Low (<V

) = logic 0; H = High (>V

) = logic 1; V

= 10.0 ± 1.0V; X = don’t care.

In ×16 mode, BYTE = V

. In ×8 mode, BYTE = V

with DQ8-DQ14 in high Z and DQ15 = A-1.

†

Verification of sector protect/unprotect during A9 = V

ID.

Mode definitions

Item

ID MFR code,

device code

Read mode

Description

Selected by A9 = V

(9.5V–10.5V), CE = OE = A1 = A6 = L, enabling outputs.

When A0 is low (V

) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products.

When A0 is high (V

), D

OUT

represents the device code for the AS29LV400.

Selected with CE = OE = L, W E = H. Data is valid in t

ACC

time after addresses are stable, t

after CE is low

and t

after O E is low.

Selected with CE = H. Part is powered down, and I

reduced to <1.0 µA when CE = V

± 0.3V = RES ET.

If activated during an automated on-chip algorithm, the device completes the operation before entering

standby.

Selected with CE

W E

= L,

O E

= H

. Accomplish all Flash erasure and programming through the command

on the falling edge of WE or C E, whichever occurs later. Data latching occurs on the rising edge WE or C E,

whichever occurs first. Filters on W E prevent spurious noise events from appearing as write commands.

Hardware protection circuitry implemented with external programming equipment causes the device to

disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector

protect algorithm on page 10.

Disables sector protection for all sectors using external programming equipment. All sectors must be

protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect

algorithm on page 10.

Verifies write protection for sector. Sectors are protected from program/erase operations on commercial

programming equipment. Determine if sector protection exists in a system by writing the ID read command

sequence and reading location XXX02h, where address bits A12–17 select the defined sector addresses. A

logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector.

Standby

Output disable Part remains powered up; but outputs disabled with O E pulled high.

Write

Enable

sector protect

Sector

unprotect

Verify sector

protect/

unprotect

7/13/01; V.0.9.8

Alliance Semiconductor

P. 4 of 21

AS29LV400

Item

Temporary

sector

unprotect

RE SE T

Deep

power down

Automatic

sleep mode

Description

Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to

RE SE T to activate temporary sector unprotect mode. During temporary sector unprotect mode, program

protected sectors by selecting the appropriate sector address. All protected sectors revert to protected state on

removal of +10V from RE SET.

Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data

may be corrupted.

Hold RESET low to enter deep power down mode (

1 µA). Recovery time to start of first read cycle is 50ns.

Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 µA. Existing data is

available to the system during this mode. If an address is changed, automatic sleep mode is disabled and new

data is returned within standard access times.

Flexible sector architecture

Bottom boot sector architecture (AS29LV400B)

Sector

×8

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

×16

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

Size

(Kbytes)

Top boot sector architecture (AS29LV400T)

×8

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–77FFFh

78000h–79FFFh

7A000h–7BFFFh

7C000h–7FFFFh

×16

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3BFFFh

3C000h–3CFFFh

3D000h–3DFFFh

Size

(Kbytes)

3E000h–3FFFFh

In word mode, there are one 8K word, two 4K word, one 16K word, and seven 32K word sectors. Address range is A17–A-1 if

B Y T E

= V

; address range is

A17–A0 if

B Y T E

= V

7/13/01; V.0.9.8

Alliance Semiconductor

P. 5 of 21

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

Recommended Resources

Y132 type end cover hydraulic press (bearing) electrical schematic diagram (2)

C523 double column vertical lathe control circuit 02

High definition! Electric bicycle circuit diagram with quantity DDL

Video recorder RF converter circuit

Photoelectric control trigger circuit

Three-phase bridge resistive load rectifier circuit

MSP430 MCU Example 21 - Timer B generates 8-channel periodic signals: 1. Task Requirements The timer B of the MSP30F247 microcontroller is used to generate 8 periodic signals with periods of 4S, 2S, 1S, 0.5, 0.25S, 0.125S, 0.0625S, and 0.03125S. The eight periodic signa...; 火辣西米秀 Microcontroller MCU

Switching power supply waveform: Hello everyone, this is the ds waveform of the single-ended forward switching power supply MOS tube. I want to know (1) How is the T1T2T3 waveform generated? (2) There is oscillation in T1, which cann...; aq1261101415 Power technology

MSP430FR2355 LaunchPad Development Kit: The MSP-EXP430FR2355 LaunchPad development kit is an easy-to-use evaluation module (EVM) based on the MSP430FR2355 Value Line microcontroller (MCU). It contains everything you need to develop on the u...; Jacktang Microcontroller MCU

6 Fusion Positioning Technologies for Wireless Communication Applications in IoT: At present, whether in indoor or outdoor environments, our demand for positioning is no longer just rough trajectory and navigation. In this era of the Internet of Everything, we urgently need to be a...; 成都亿佰特 Test/Measurement

PlainDAQ data logger based on Raspberry Pi Pico: PlainDAQ turns your Raspberry Pi Pico into a simple, sophisticated 4-channel oscilloscope and single-channel function generator.Project website:[hide]https://github.com/AlperenAkkuncu/PlainDAQ[/hide]...; dcexpert MicroPython Open Source section

EEWORLD University----Live Replay: Microchip Security Series 21 - Secure Boot and Message Authentication for CAN FD in ADAS and IVI Systems Using TA100-VAO: Live Replay: Microchip Security Series 21 - Secure Boot and Message Authentication for CAN FD in ADAS and IVI Systems Using TA100-VAO : https://training.eeworld.com.cn/course/67795...; hi5 Integrated technical exchanges

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components