4K
X25057
DESCRIPTION
512 x 8 Bit
5MHz Low Power SPI Serial E
2
PROM with IDLock™ Memory
FEATURES
• 5MHz Clock Rate
• IDLock™ Memory
—IDLock First or Last Page, Any 1/4 or Lower 1/2
of E
2
PROM Array
• Low Power CMOS
—<1
µ
A Standby Current
—<3mA Active Current during Write
—<400
µ
A Active Current during Read
• 1.8V to 3.6V, 2.7V-5.5V or 4.5V to 5.5V Operation
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• SPI Modes (0,0 & 1,1)
• 512 x 8 Bits
—16 Byte Page Mode
• Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 Cycles/Byte
—Data Retention: 100 Years
—ESD: 2000V on all pins
• 8-Lead MSOP Package
• 8-Lead TSSOP Package
• 8-Lead SOIC Package
• 8-Lead PDIP Package
FUNCTIONAL DIAGRAM
SI
SO
COMMAND
DECODE
AND
CONTROL
LOGIC
DATA REGISTER
Y DECODE LOGIC
16
SCK
X
DECODE
LOGIC
32
8
The X25057 is a CMOS 4K-bit serial E
2
PROM, internally
organized as 512 x 8. The X25057 features a Serial
Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
IDLock is a programmable locking mechanism which
allows the user to lock system ID and parametric data in
different portions of the E
2
PROM memory space,
ranging from as little as one page to as much as 1/2 of
the total array. The X25057 also features a WP pin that
can be used for hardwire protection of the part, disabling
all write attempts, as well as a Write Enable Latch that
must be set before a write operation can be initiated.
The X25057 utilizes Xicor’s proprietary Direct Write
TM
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
4K E
2
PROM
ARRAY
(512 x 8)
CS
WP
WRITE CONTROL LOGIC
HIGH VOLTAGE
CONTROL
7033 FRM F01
©
Xicor, Inc. 1994 – 1997 Patents Pending
7033-1.1 5/8/97 T1/C0/D0 SH
1
Characteristics subject to change without notice
X25057
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is a serial data input pin. All opcodes, byte addresses,
and data to be written to the memory are input on this
pin. Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
When CS is HIGH, the X25057 is deselected and the SO
output pin is at high impedance and unless an internal
write operation is underway, the X25057 will be in the
standby power mode. CS LOW enables the X25057,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Write Protect (WP)
When WP is LOW, nonvolatile writes to the X25057 are
disabled, but the part otherwise functions normally. When
WP is held HIGH, all functions, including nonvolatile
writes operate normally. WP going LOW while CS is still
LOW will interrupt a write to the X25057. If the internal
write cycle has already been initiated, WP going low will
have no affect on this write.
PIN NAMES
Symbol
CS
SO
SI
SCK
WP
V
SS
V
CC
NC
CS
SO
*0.197"
WP
V SS
PIN CONFIGURATION
Not to scale
8 Lead SOIC/PDIP
1
2
3
4
*0.244"
8 Lead MSOP
SO
CS
0.120"
VSS
WP
1
2
3
4
0.193"
8 Lead TSSOP
NC
0.122"
VCC
CS
SO
1
2
3
4
0.252"
*SOIC Measurement
X25057
8
7
6
5
SCK
SI
V SS
WP
7033 FRM F02.2
8
7
X25057
6
5
V CC
NC
SCK
SI
7033 FRM F02
8
7
X25057
6
5
V CC
NC
SI
SCK
7033 FRM F02.1
PRINCIPLES OF OPERATION
The X25057 is a 512 x 8 E
2
PROM designed to interface
directly with the synchronous Serial Peripheral Interface
(SPI) of many popular microcontroller families.
The X25057 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS must be LOW and the WP
input must be HIGH during the entire operation. Table 1
contains a list of the instructions and their opcodes. All
instructions, addresses and data are transferred MSB first.
Data input is sampled on the first rising edge of SCK
after CS goes LOW. SCK is static, allowing the user to
stop the clock and then start it again to resume opera-
tions where left off.
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
No Connect
7033 FRM T01
2
X25057
Write Enable Latch
The X25057 contains a “Write Enable” latch. This latch
must be SET before a write operation is initiated. The
WREN instruction will set the latch and the WRDI instruc-
tion will reset the latch (Figure 4). This latch is automati-
cally reset upon a power-up condition and after the
completion of a byte or page write cycle.
IDLock Memory
Xicor’s IDLock Memory provides a flexible mechanism to
store and lock system ID and parametric information.
There are seven distinct IDLock Memory areas within the
array which vary in size from one page to as much as half
of the entire array. These areas and associated address
ranges are IDLocked by writing the appropriate two byte
IDLock instruction to the device as described in Table 1
and Figure 7. Once an IDLock instruction has been com-
pleted, that IDLock setup is held in a nonvolatile Status
Register (Figure 1) until the next IDLock instruction is
issued. The sections of the memory array that are
IDLocked can be read but not written until IDLock is
removed or changed.
Figure 1. Status Register/IDLock Protection Byte
7
0
6
0
5
0
4
0
3
0
2
1
0
IDL2 IDL1 IDL0
7038 FRM T02.1
Read Status Operation
If there is not a nonvolatile write in progress, the Read
Status instruction returns the ID Lock byte from the Sta-
tus Register which contains the ID Lock bits IDL2-IDL0
(Figure 1). The ID Lock bits define the ID Lock condition
(Figure 1/Table1). The other bits are reserved and will
return ’0’ when read. See Figure 3.
If a nonvolatile write is in progress, the Read Status
Instruction returns a HIGH on SO. When the nonvolatile
write cycle is completed, the status register data is read
out.
Clocking SCK is valid during a nonvolatile write in
progress, but is not necessary. If the SCK line is clocked,
the pointer to the status register is also clocked, even
though the SO pin shows the status of the nonvolatile
write operation (See Figure 3).
Write Sequence
Prior to any attempt to write data into the X25057, the
“Write Enable” latch must first be set by issuing the
WREN instruction (See Table 1 and Figure 4). CS is first
taken LOW. Then the WREN instruction is clocked into
the X25057. After all eight bits of the instruction are
transmitted, CS must then be taken HIGH. If the user
continues the write operation without taking CS HIGH
after issuing the WREN instruction, the write operation
will be ignored.
To write data to the E
2
PROM memory array, the user then
issues the WRITE instruction, followed by the 16 bit
address and the data to be written. Only the last 9 bits of
the address are used and bits [15:9] are specified to be
zeroes. This is minimally a thirty-two clock operation. CS
must go LOW and remain LOW for the duration of the
operation. The host may continue to write up to 16 bytes
of data to the X25057. The only restriction is the 16 bytes
must reside on the same page. If the address counter
reaches the end of the page and the clock continues, the
counter will “roll over” to the first address of the page and
overwrite any data that may have been previously written.
For a byte or page write operation to be completed, CS
can only be brought HIGH after bit 0 of the last data byte
to be written is clocked in. If it is brought HIGH at any
other time, the write operation will not be completed.
Refer to Figures 5 and 6 for detailed illustration of the
write sequences and time frames in which CS going
HIGH are valid.
Note: Bits [7:3] specified to be “0’s”
Clock and Data Timing
Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
SCK.
Read Sequence
When reading from the E
2
PROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25057, followed by the
16-bit address, of which the last 9 bits are used (bits
[15:9] specified to be zeroes). After the READ opcode
and address are sent, the data stored in the memory at
the selected address is shifted out on the SO line. The
data stored in memory at the next address can be read
sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next higher
address after each byte of data is shifted out. When the
highest address is reached (01FFh), the address counter
rolls over to address 0000h, allowing the read cycle to be
continued indefinitely. The read operation is terminated
by taking CS HIGH. Refer to the Read Operation
Sequence illustrated in Figure 2.
3
X25057
IDLock Operation
Prior to any attempt to perform an IDLock Operation, the
WREN instruction must first be issued. This instruction
sets the “Write Enable” latch and allows the part to
respond to an IDLock sequence (Figure 7). The IDLock
instruction follows and consists of one command byte fol-
lowed by one IDLock byte (See Figure 1). This byte con-
tains the IDLock bits IDL2-IDL0. The rest of the bits [7:3]
are unused and must be written as zeroes. Bringing CS
HIGH after the two byte IDLock instruction initiates a
nonvolatile write to the Status Register. Writing more
than one byte to the Status Register will overwrite the
previously written IDLock byte. See Table 1.
Operational Notes
The X25057 powers up in the following state:
• The device is in the low power, standby state.
• A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
• SO pin is at high impedance.
• The “Write Enable” latch is reset.
Data Protection
The following circuitry has been included to prevent inad-
vertant writes:
• The “Write Enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “Write
Enable” latch.
• CS must come HIGH at the proper clock count in order
to start a write cycle.
Table 1. Instruction Set and Block Lock Protection Byte Definition
Instruction Format*
0000 0110
0000 0100
0000 0001
Instruction Name and Operation
WREN: Set the Write Enable Latch (Write Enable Operation)
WRDI: Reset the Write Enable Latch (Write Disable Operation)
IDLock Instruction—followed by:
IDLock Byte: (See Figure 1)
0000 0000 --->NO IDLock: 00h-00h ---------->None of the Array
0000 0001 --->IDLock Q1: 00h-7Fh ---------->Lower Quadrant (Q1)
0000 0010 --->IDLock Q2: 80h-FFh----------->Q2
0000 0011 --->IDLock Q3: 100h-17Fh-------->Q3
0000 0100 --->IDLock Q4: 180h-1FFh-------->Upper Quadrant (Q4)
0000 0101 --->IDLock H1: 00h-FFh----------->Lower Half of the Array (H1)
0000 0110 --->IDLock P0: 0h-Fh-------------->Lower Page (P0)
0000 0111 --->IDLock Pn: 1F0h-1FFh-------->Upper Page (Pn)
READ STATUS: Reads IDLock & write in progress status on SO Pin
WRITE: Write operation followed by address and data
READ: Read operation followed by address
7033 FRM T03
0000 0101
0000 0010
0000 0011
*Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
4
X25057
Figure 2. Read Operation Sequence
CS
0
SCK
1
2
3
4
5
6
7
8
9
20 21 22 23 24 25 26 27 28 29 30
READ INSTRUCTION
(1 BYTE)
SI
BYTE ADDRESS (2 BYTE)
15 14
3
2
1
0
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
7033 FRM F03.1
Figure 3. Read Status Operation Sequence
CS
0
SCK
1
2
3
4
5
6
7
...
...
I
D
L
2
I
D
L
1
I
D
L
0
READ STATUS
INSTRUCTION
SI
NONVOLATILE WRITE IN PROGRESS
SO
...
SO HIGH DURING
NONVOLATILE
WRITE CYCLE
SO = STATUS REG BIT
WHEN NO NONVOLATILE
WRITE CYCLE
7033 FRM F04.2
5
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