Integrated
Circuit
Systems, Inc.
Product Data Sheet
M902-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
XTAL_1 / REF_IN
GND
STOP
EXT_CLK
EN_EXT_CLK
NC
NC
NC
VCC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M902-01 is a PLL (Phase Locked Loop) based
clock generator that uses an
internal VCSO (Voltage Controlled
SAW Oscillator) to produce a very
low jitter output clock. It is ideal for
Gigabit Ethernet. The output clock
(frequency of
156.25
or
187.50
MHz
for example) is provided from two
LVPECL clock output pairs. (Specify frequency at time
of order.) The accuracy of the output frequency is
assured by the internal PLL, which phase-locks the
internal VCSO to the reference input frequency (
25
or
30
MHz for example). The input reference can either
be an external crystal, utilizing the internal crystal
oscillator, or a stable external clock source such as
a packaged crystal oscillator.
XTAL_2
NC
NC
NC
NC
VCC
DNC
DNC
DNC
28
29
30
31
32
33
34
35
36
M902-01
(Top View)
18
17
16
15
14
13
12
11
10
NC
NC
nFOUT1
FOUT1
GND
nFOUT0
FOUT0
VCC
GND
F
EATURES
◆
Output clock frequency from 125MHz to 190MHz
(Consult factory for frequency availability)
◆
Two identical LVPECL output pairs
◆
Integrated SAW (surface acoustic wave) delay line
◆
Low jitter 0.5ps rms (over 12kHz-20MHz)
◆
Ideal for Gigabit Ethernet clock reference
◆
Output-to-output skew < 100ps
◆
External XTAL or LVCMOS reference input
◆
Selectable external feed-through clock input
◆
STOP
clock control (Logic 1 stops output clocks)
◆
Industrial temperature grade available
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
Figure 1: Pin Assignment
Example Output Frequency Configurations
Ref Clock
Frequency
(MHz)
20
25
30
25/4
PLL
Ratio
Output
Frequency
1
(MHz)
125.00
156.25
187.50
Application
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
GbE
10GbE
12GbE
Table 1: Example Output Frequency Configurations
Note 1: Specify output clock frequency at time of order
S
IMPLIFIED
B
LOCK
D
IAGRAM
M902-01
VSCO
External
Crystal
or
Reference
Clock Input
(e.g., 25 or 30MHz)
XTAL
OSC
Divider
Frequency
Multiplying
PLL
O
1
LVPECL
Output
Clock Pairs
(e.g., 156.25
or 187.50MHz)
External
Loop Filter
External
Clock
Input
External
Clock
Select
Output
Clock STOP
Control
Figure 2: Simplified Block Diagram
M902-01 Datasheet Rev 2.1
M902-01 VCSO Based GbE Clock Generator
Revised 24Jun2004
●
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
Networking & Communications
●
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Integrated
Circuit
Systems, Inc.
M902-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
Product Data Sheet
D
ETAILED
B
LOCK
D
IAGRAM
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
C
LOOP
OP_OUT
R
POST
nOP_OUT
nVC
VC
External
Loop Filter
Components
M902-01
Phase
Detector
OP_IN
nOP_IN
XTAL_1 / REF_IN
XTAL_2
R
IN
SAW Delay Line
XTAL
OSC
R Divider
R=4
R
IN
Loop Filter
Amplifier
Phase
Shifter
VCSO
M Divider
M = 25
O
Phase Locked Loop (PLL)
EXT_CLK
EN_EXT_CLK
STOP
1
FOUT1
nFOUT1
FOUT0
nFOUT0
Figure 3: Detailed Block Diagram
P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
11, 19, 33
12
13
15
16
17, 18
20, 21, 22
29, 30, 31, 32
23
24
25
27
28
34, 35, 36
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
FOUT0
nFOUT0
FOUT1
nFOUT1
NC
I/O
Configuration
Description
Ground
Input
Output
Input
Power
Output
No internal terminator
Power supply ground connections.
External loop filter connections. See Figure 5,
External Loop Filter, on pg. 4.
Power supply connection, connect to +
3.3
V.
Clock output pairs, differential LVPECL output
(
156.25
MHz for the
M902-01-156.2500
)
No internal connection
EN_EXT_CLK
EXT_CLK
STOP
XTAL_1 / REF_IN
XTAL_2
DNC
Input
Input
Input
Input
Input
Logic
1
enables the
EXT_CLK
input.
Use Logic
0
for normal operation.
External clock feed-through:
0
to
200
MHz
Logic
1
stops clock outputs.
Internal pull-down resistor
1
Use Logic
0
for normal operation.
External crystal connection. Also accepts
LVCMOS/LVTTL compatible clock source.
External crystal connection. Leave unconnected
when driving pin
27
with external clock reference.
Do Not Connect.
Internal pull-down resistor
1
Table 2: Pin Descriptions
Note 1: For typical value of internal pull-down resistor, see DC Characteristics, Pull-down on pg. 6.
M902-01 Datasheet Rev 2.1
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
2 of 8
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●
Revised 24Jun2004
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Integrated
Circuit
Systems, Inc.
M902-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
Product Data Sheet
The PLL
The PLL (Phase Locked Loop) includes the phase
detector, the VCSO, a feedback divider (labeled
“M Divider”), and a reference divider (“R Divider”).
The feedback divider divides the VCSO output
frequency by a fixed value “M” to match the reference
frequency provided to the phase detector by the
reference divider.
By controlling the frequency and phase of the VCSO,
the phase detector precisely locks the frequency and
phase of the feedback divider output to that of the
reference divider output.
The relationship between the VCSO output frequency,
the M Divider, the R Divider and the input reference
frequency is defined as follows:
M
-
Fvcso = Fxtal
×
----
R
For the
M902-01-156.2500
(see “Ordering Information” on pg. 8):
F
UNCTIONAL
D
ESCRIPTION
The M902-01 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock.
The M902-01 combines the flexibility of a VCSO
(Voltage Controlled SAW Oscillator) with the stability of
a crystal oscillator.
Input Reference
The input reference can either be an external, discrete
crystal or a stable external clock source such as a
packaged (temperature-compensated) crystal
oscillator.
•
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should be a parallel-resonant, fundamental mode
crystal. Apply it to the
XTAL_1 / REF_IN
and
XTAL_2
input
pins. External crystal load trim capacitors are also
required. (See “Crystal Specifications” on pg. 4.)
•
If an external LVCMOS/LVTTL clock source is used,
apply it to the
XTAL_1 / REF_IN
input pin.
In either case, the reference clock is supplied to the
phase detector of the PLL. The M902-01 includes a
reference divider that divides the input reference
frequency by a fixed value “R” and provides the result to
the phase detector.
The
EX_CLK
pin is available for a clock feed-through
mode for testing. See “External Clock Feed-through”
on pg. 3.
•
•
•
•
VCSO output frequency = 156.25MHz
Input reference frequency = 25MHz
M=25
R= 4
Therefore, for the
M902-01-156.2500
:
25
-
156.25MHz = 25MHz
×
---------
4
M
-
The product of the input crystal frequency and ----
R
falls within the lock range of the VCSO.
External Clock Feed-through
The
EXT_CLK
pin provides an input for an external
single-ended clock that directly drives the LVPECL
clock outputs. This pin is intended for system debugging
and performance evaluation..
EN_EXT_CLK
EXT_CLK
Logic
1
enables the
EXT_CLK
input.
Use Logic
0
for normal operation.
Apply an external LVCMOS/LVTTL clock source
for
0
to
200
MHz feed-through operation.
Leave inactive for normal operation.
1
Note 1: In applications where EXT_CLK is active while the SAW PLL
signal path is enabled, it is necessary to gate the EXT_CLK to
minimize jitter in the LVPECL output pairs. See the
PCB Design
Guidelines for ICS SAW PLLs
application note at
www.icst.com/products/appnotes/M000-AN-001.PCBdesign.pdf
STOP Clock
The
STOP
pin puts the output clock into a static condition.
Logic 1 Output clocks are static
Logic 0 Output clocks enabled for normal operation
M902-01 Datasheet Rev 2.1
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
3 of 8
Networking & Communications
●
Revised 24Jun2004
w w w. i c s t . c o m
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tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M902-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
Product Data Sheet
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M902-01 requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 5).
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
OP_IN
nOP_IN
4
9
A
PPLICATION
I
NFORMATION
This section includes information on the optional
external crystal and on the external loop filter.
The subsections on the loop filter provide example
component values and also briefly describe the SAW
PLL simulator tool and additional application
information available at www.icst.com.
External Crystal Specifications
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should have the following general specifications:
Crystal Specifications
Parameter
Min Typ Max Unit
AT-cut quartz
Fundamental
16
40
C
LOOP
OP_OUT
8
5
R
POST
nOP_OUT
nVC
6
7
VC
Figure 5: External Loop Filter
f
0
∆
f/f
0
Crystal Type
Mode of Oscillation
Nominal Frequency Range
Frequency Tolerance @
+25
o
C
1
MHz
ppm
ppm
ppm
±
15
±
50
±
5
50
7
∆
f/f
C
/ T
A
Frequency Stability
-40 to +85
o
C
1
∆
f/f
0
/ y Aging, per year (first) @
+25
o
C
1
ESR
The loop filter is implemented as a differential circuit
to minimize system noise interference. Due to the
differential signal path design, the implementation
requires two identical complementary RC filters as
shown here. See Table 4, External Loop Filter
Component Values, below.
External Loop Filter Component Values
PLL Bandwidth Damping R loop C loop R post C post
Factor
(
kΩ
)
(
µF
)
(
kΩ
)
(
pF
)
(
kHz
)
0.5
1.5
1
2.1
2
6.4
10.6
3
3.0
3.3
1.1
4.5
4.2
1.5
4.7
4.7
20.0
33.0
4.70
1.00
0.10
0.10
0.03
20
10
10
20
20
150
150
150
270
120
C
S
C
L
P
0
Equivalent Series Resistance
Shunt Capacitance
Spurious Response (non-harmonic)
Load Capacitance,
parallel load resonant
Drive Level
16
0.1
Ω
pF
-
40
dBc
32
1.0
pF
mW
Table 3: External Loop Filter Component Values
Note 1: These frequency tolerance specifications are suitable for
a
±100
ppm clock output frequency requirement.
Table 4: External Loop Filter Component Values
The external crystal will be applied to the
XTAL_1 / REF_IN
and
XTAL_2
input pins. External crystal load capacitors
are also required.
Recommended External Crystal Configuration
M902-01
M9xx-0x
XTAL_1 / REF_IN
C1
Note 1: Optimum loop bandwidth when using an external reference
crystal. Will help to attenuate interference on the crystal’s
sinusoidal clock waveform and therefore will minimize
device output clock jitter.
Note 2: Alternative loop filter setting when using an external refer-
ence crystal. Smaller C loop lowers loop damping factor with
negligible increase in output jitter.
Note 3: Optimum loop bandwidth when using an external reference
crystal oscillator. The square wave clock reference does not
require as much jitter attenuation, which allows for a wider
loop bandwidth and improved system noise tolerance.
XTAL
XTAL_2
C2
XTAL OSC
Refer to the M902-01 product web page at
www.icst.com/products/summary/m902-01.htm for
additional product information.
Figure 4: Recommended External Crystal Configuration
XTAL= 25 or 30 MHz, Load Capacitance Specification = 18 pF
C1 = 27 pF
C2 = 33 pF
External load capacitors C1 and C2 present a load of 15 pf
to the crystal (they are seen in series by the crystal through
the common ground connection). With the additional of PCB
trace capacitance and M902-01 input capacitance, the total
load to the crystal is about 18 pf.
M902-01 Datasheet Rev 2.1
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
4 of 8
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Revised 24Jun2004
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Integrated
Circuit
Systems, Inc.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
Refer to the SAW PLL Simulator Software web page at
www.icst.com/products/calculators/m2000filterSWdesc.htm
for additional information.
M902-01
VCSO B
ASED
G
B
E C
LOCK
G
ENERATOR
Product Data Sheet
SAW PLL Application Notes Available
The ICS web site (www.icst.com) also has application
notes on:
•
PCB layout guidelines (including special detailed
•
•
•
instructions for preventing issues such as external
reference crosstalk)
Any new special device application details that may
become available
Instructions for using PLL simulator software
Guidelines for PCB fabrication (including recom-
mended PCB footprint, solder mask, and furnace
profile)
Refer to the SAW PLL Application Notes web page at
www.icst.com/products/appnotes/SawPllAppNotes.htm
for application notes and any additional product
information that may become available.
A
BSOLUTE
M
AXIMUM
R
ATINGS1
Symbol Parameter
Rating
Unit
V
I
V
O
I
O
V
CC
T
S
Input Voltage
Output Voltage
Output Current
Power Supply Voltage
Storage Temperature
-
0.5
to V
CC
+
0.5
-
0.5
to V
CC
+
0.5
25
4.6
V
V
mA
V
o
-
45
to +
100
C
Table 5: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
R
ECOMMENDED
C
ONDITIONS OF
O
PERATION
Symbol Parameter
Min
3.135
Typ
3.3
Max
3.465
Unit
V
CC
T
A
Positive Supply Voltage
Ambient Operating Temperature
Commercial
Industrial
V
o
C
o
C
0
-40
+
70
+
85
Table 6: Recommended Conditions of Operation
M902-01 Datasheet Rev 2.1
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
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Revised 24Jun2004
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