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NS32AM163V-20

Description
IC 16-BIT, 40.96 MHz, OTHER DSP, PQCC68, PLASTIC, LCC-68, Digital Signal Processor
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size746KB,80 Pages
ManufacturerNational Semiconductor(TI )
Websitehttp://www.ti.com
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NS32AM163V-20 Overview

IC 16-BIT, 40.96 MHz, OTHER DSP, PQCC68, PLASTIC, LCC-68, Digital Signal Processor

NS32AM163V-20 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerNational Semiconductor(TI )
package instructionQCCJ,
Reach Compliance Codeunknown
ECCN code3A001.A.3
Address bus width18
boundary scanNO
maximum clock frequency40.96 MHz
External data bus width16
FormatFIXED POINT
Integrated cacheNO
Internal bus architectureSINGLE
JESD-30 codeS-PQCC-J68
JESD-609 codee0
length24.13 mm
low power modeYES
Number of DMA channels
Number of external interrupt devices1
Number of serial I/Os
Number of terminals68
Number of timers1
On-chip data RAM width8
On-chip program ROM width8
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
RAM (number of words)1075.2
ROM programmabilityMROM
Maximum seat height4.57 mm
Maximum slew rate200 mA
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width24.13 mm
uPs/uCs/peripheral integrated circuit typeDIGITAL SIGNAL PROCESSOR, OTHER

NS32AM163V-20 Related Products

NS32AM163V-20 NS32AM162V-20
Description IC 16-BIT, 40.96 MHz, OTHER DSP, PQCC68, PLASTIC, LCC-68, Digital Signal Processor IC 16-BIT, 40.96 MHz, OTHER DSP, PQCC68, PLASTIC, LCC-68, Digital Signal Processor
Is it Rohs certified? incompatible incompatible
Maker National Semiconductor(TI ) National Semiconductor(TI )
package instruction QCCJ, QCCJ,
Reach Compliance Code unknown unknown
ECCN code 3A001.A.3 3A001.A.3
Address bus width 18 18
boundary scan NO NO
maximum clock frequency 40.96 MHz 40.96 MHz
External data bus width 16 16
Format FIXED POINT FIXED POINT
Integrated cache NO NO
Internal bus architecture SINGLE SINGLE
JESD-30 code S-PQCC-J68 S-PQCC-J68
JESD-609 code e0 e0
length 24.13 mm 24.13 mm
low power mode YES YES
Number of external interrupt devices 1 1
Number of terminals 68 68
Number of timers 1 1
On-chip data RAM width 8 8
On-chip program ROM width 8 8
Maximum operating temperature 70 °C 70 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code QCCJ QCCJ
Package shape SQUARE SQUARE
Package form CHIP CARRIER CHIP CARRIER
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED
Certification status Not Qualified Not Qualified
RAM (number of words) 1075.2 1075.2
ROM programmability MROM MROM
Maximum seat height 4.57 mm 4.57 mm
Maximum slew rate 200 mA 200 mA
Maximum supply voltage 5.5 V 5.5 V
Minimum supply voltage 4.5 V 4.5 V
Nominal supply voltage 5 V 5 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form J BEND J BEND
Terminal pitch 1.27 mm 1.27 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 24.13 mm 24.13 mm
uPs/uCs/peripheral integrated circuit type DIGITAL SIGNAL PROCESSOR, OTHER DIGITAL SIGNAL PROCESSOR, OTHER

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