IC,LOGIC GATE,2 2/2-IN AND-NOR,CMOS, RAD HARD,DIP,14PIN,CERAMIC
Parameter Name | Attribute value |
Is it Rohs certified? | incompatible |
Maker | Renesas Electronics Corporation |
package instruction | DIP, DIP14,.3 |
Reach Compliance Code | not_compliant |
JESD-30 code | R-XDIP-T14 |
JESD-609 code | e0 |
Load capacitance (CL) | 50 pF |
Logic integrated circuit type | AND-OR-INVERT GATE |
MaximumI(ol) | 0.00036 A |
Number of terminals | 14 |
Maximum operating temperature | 125 °C |
Minimum operating temperature | -55 °C |
Package body material | CERAMIC |
encapsulated code | DIP |
Encapsulate equivalent code | DIP14,.3 |
Package shape | RECTANGULAR |
Package form | IN-LINE |
power supply | 5/15 V |
Prop。Delay @ Nom-Sup | 837 ns |
Certification status | Not Qualified |
Schmitt trigger | NO |
Filter level | 38535V;38534K;883S |
surface mount | NO |
technology | CMOS |
Temperature level | MILITARY |
Terminal surface | Tin/Lead (Sn/Pb) |
Terminal form | THROUGH-HOLE |
Terminal pitch | 2.54 mm |
Terminal location | DUAL |
total dose | 1M Rad(Si) V |