530BB730M000DGR datasheet, PDF

530BB730M000DGR: DescriptionLVDS Output Clock Oscillator, 730MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530BB730M000DGR Overview

LVDS Output Clock Oscillator, 730MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	730 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVDS
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)

How to enable TI 15.4-Stack to support 470M frequency band: [align=left][size=4][color=#000000][backcolor=white]TI 15.4-Stack is an IEEE 802.15.4e/g RF communication stack. It is an integral part of the SimpleLink CC13xx/CC26x2 Software Development Kit (SDK) a...; Aguilera Wireless Connectivity

An error occurred when generating a bit file. Could you please give me some advice?: ...; lym1210 FPGA/CPLD

Detailed explanation of the voltage following circuit of the operational amplifier: [i=s]This post was last edited by fish001 on 2019-11-13 22:28[/i]The voltage following circuit of an op amp, as shown in Figure 1, uses virtual short and virtual open circuits. It looks simple and cle...; fish001 Analogue and Mixed Signal

USB to canfd analysis and development: The hardware uses stm32h72x+usb3300+ata6563+tja1020 andthe software uses qt+usblib. Two canfd and two LIN busesComplete the basic message sending and receiving functions. The host computer is currentl...; afei9527 stm32/stm8

Verilog HDL Comprehensive Practical Tutorial.pdf: Verilog HDL Comprehensive Practical Tutorial.pdf...; zxopenljx EE_FPGA Learning Park

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components