SJ80C52XXX-36 datasheet, PDF - EEWORLD Datasheet

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SJ80C52XXX-36: DescriptionMicrocontroller, 8-Bit, MROM, 36MHz, CMOS, LCC-44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size284KB，20 Pages; ManufacturerTEMIC; Websitehttp://www.temic.de/

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SJ80C52XXX-36 Overview

Microcontroller, 8-Bit, MROM, 36MHz, CMOS, LCC-44

SJ80C52XXX-36 Parametric

Parameter Name	Attribute value
Maker	TEMIC
package instruction	LCC-44
Reach Compliance Code	unknown
Has ADC	NO
Address bus width	16
bit size	8
maximum clock frequency	44 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	S-XQCC-J44
Number of I/O lines	32
Number of terminals	44
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
PWM channel	NO
Package body material	UNSPECIFIED
Package shape	SQUARE
Package form	CHIP CARRIER
Certification status	Not Qualified
ROM programmability	MROM
speed	36 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	J BEND
Terminal location	QUAD
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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80C32/80C52/80C32E

CMOS 0 to 36 MHz Single Chip 8–bit Microcontroller

1. Description

TEMIC’s 80C52 and 80C32 are high performance CMOS versions of the 8052/8032 NMOS single chip 8 bit

Microcontroller.

The fully static design of the TEMIC 80C52/80C32 allows to reduce system power consumption by bringing the clock

frequency down to any value, even DC, without loss of data.

The 80C52 retains all the features of the 8052: 8 K bytes of ROM; 256 bytes of RAM; 32 I/O lines; three 16 bit timers;

a 6-source, 2-level interrupt structure; a full duplex serial port; and on-chip oscillator and clock circuits. In addition,

the 80C52 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle

mode the CPU is frozen while the RAM, the timers, the serial port and the interrupt system continue to function. In

the power down mode the RAM is saved and all other functions are inoperative.

The 80C32 is identical to the 80C52 except that it has no on-chip ROM. TEMIC’s 80C52/80C32 are manufactured

using SCMOS process which allows them to run from 0 up to 36 MHz with VCC = 5 V.

D

D

D

D

D

80C32: Romless version of the 80C52

80C32/80C52-12: 0 to 12 MHz

80C32/80C52-30: 0 to 30 MHz

80C32/80C52-36: 0 to 36 MHz

80C32E-30: 0 to 30 MHz Radiation Tolerant

2. Features

D

D

D

D

D

D

D

Power control modes

256 bytes of RAM

8 Kbytes of ROM (80C52)

32 programmable I/O lines

Three 16 bit timer/counters

64 K program memory space

64 K data memory space

Rev. J

–

July 03, 2000

1

80C32/80C52/80C32E

4. Pin Description

4.1. VSS

Circuit ground potential.

4.2. VCC

Supply voltage during normal, Idle, and Power Down operation.

4.3. Port 0

Port 0 is an 8 bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in that state can

be used as high-impedance inputs.

Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory.

In this application it uses strong internal pullups when emitting 1’s. Port 0 also outputs the code bytes during program

verification in the 80C52. External pullups are required during program verification. Port 0 can sink eight LS TTL

inputs.

4.4. Port 1

Port 1 is an 8 bit bi-directional I/O port with internal pullups. Port 1 pins that have 1’s written to them are pulled high

by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled

low will source current (IIL, on the data sheet) because of the internal pullups.

Port 1 also receives the low-order address byte during program verification. In the 80C52, Port 1 can sink/ source three

LS TTL inputs. It can drive CMOS inputs without external pullups.

2 inputs of PORT 1 are also used for timer/counter 2 :

P1.0 [T2]: External clock input for timer/counter 2. P1.1 [T2EX]: A trigger input for timer/counter 2, to be reloaded

or captured causing the timer/counter 2 interrupt.

4.5. Port 2

Port 2 is an 8 bit bi-directional I/O port with internal pullups. Port 2 pins that have 1’s written to them are pulled high

by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled

low will source current (ILL, on the data sheet) because of the internal pullups. Port 2 emits the high-order address

byte during fetches from external Program Memory and during accesses to external Data Memory that use 16 bit

addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1’s. During accesses to

external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function

Register.

It also receives the high-order address bits and control signals during program verification in the 80C52. Port 2 can

sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.

4.6. Port 3

Port 3 is an 8 bit bi-directional I/O port with internal pullups. Port 3 pins that have 1’s written to them are pulled high

by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled

low will source current (ILL, on the data sheet) because of the pullups. It also serves the functions of various special

features of the TEMIC 51 Family, as listed below.

4

Rev. J

–

July 03, 2000

80C32/80C52/80C32E

Port Pin

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

Alternate Function

RXD (serial input port)

TXD (serial output port)

INT0 (external interrupt 0)

INT1 (external interrupt 1)

TD (Timer 0 external input)

T1 (Timer 1 external input)

WR (external Data Memory write strobe)

RD (external Data Memory read strobe)

Port 3 can sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.

4.7. RST

A high level on this for two machine cycles while the oscillator is running resets the device. An internal pull-down

resistor permits Power-On reset using only a capacitor connected to VCC. As soon as the Reset is applied (Vin), PORT

1, 2 and 3 are tied to one. This operation is achieved asynchronously even if the oscillator does not start-up.

4.8. ALE

Address Latch Enable output for latching the low byte of the address during accesses to external memory. ALE is

activated as though for this purpose at a constant rate of 1/6 the oscillator frequency except during an external data

memory access at which time one ALE pulse is skipped. ALE can sink/source 8 LS TTL inputs. It can drive CMOS

inputs without an external pullup.

4.9. PSEN

Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each machine

cycle during fetches from external Program Memory. (However, when executing out of external Program Memory, two

activations of PSEN are skipped during each access to external Data Memory). PSEN is not activated during fetches

from internal Program Memory. PSEN can sink/source 8 LS TTL inputs. It can drive CMOS inputs without an external

pullup.

4.10. EA

When EA is held high, the CPU executes out of internal Program Memory (unless the Program Counter exceeds 1

FFFH). When EA is held low, the CPU executes only out of external Program Memory. EA must not be floated.

4.11. XTAL1

Input to the inverting amplifier that forms the oscillator. Receives the external oscillator signal when an external

oscillator is used.

Output of the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator is used.

Rev. J

–

July 03, 2000

5

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