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CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through
SRAM with NoBL™ Architecture
Features
■
■
■
■
■
■
■
■
■
Functional Description
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
are 3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through
burst SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471BV33, CY7C1473BV33, and
CY7C1475BV33 are equipped with the advanced No Bus
Latency (NoBL) logic. NoBL™ is required to enable consecutive
read or write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput of
data through the SRAM, especially in systems that require
frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
Write operations are controlled by two or four Byte Write Select
(BW
X
) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence. For best practice recommendations,
refer to the Cypress application note
AN1064
“SRAM System
Guidelines”.
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte Write capability
3.3V/2.5V IO supply (V
DDQ
)
Fast clock-to-output times
❐
6.5 ns (for 133 MHz device)
Clock Enable (CEN) pin to enable clock and suspend operation
Synchronous self-timed writes
Asynchronous Output Enable (OE)
CY7C1471BV33, CY7C1473BV33 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-Ball FBGA package. CY7C1475BV33
available in Pb-free and non-Pb-free 209-Ball FBGA package
Three Chip Enables (CE
1
, CE
2
, CE
3
) for simple depth
expansion
Automatic power down feature available using ZZ mode or CE
deselect
IEEE 1149.1 JTAG Boundary Scan compatible
Burst Capability—linear or interleaved burst order
Low standby power
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Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
133 MHz
6.5
305
120
117 MHz
8.5
275
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document #: 001-15029 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 05, 2008
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