DDR SDRAM 512Mb C-die (x4, x8, x16)
512Mb C-die Revision History
Revision 0.0 (October, 2004)
- First version for internal review
Preliminary
DDR SDRAM
Rev. 0.0 October. 2004
DDR SDRAM 512Mb C-die (x4, x8, x16)
Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60Ball FBGA
Pb-Free
package
•
RoHS compliant
Preliminary
DDR SDRAM
Ordering Information
Part No.
K4H510438C-ZC/LCC
K4H510438C-ZC/LB3
K4H510438C-ZC/LA2
K4H510438C-ZC/LB0
K4H510838C-ZC/LCC
K4H510838C-ZC/LB3
K4H510838C-ZC/LA2
K4H510838C-ZC/LB0
K4H511638C-ZC/LCC
K4H511638C-ZC/LB3
K4H511638C-ZC/LA2
K4H511638C-ZC/LB0
32M x 16
64M x 8
128M x 4
Org.
Max Freq.
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
SSTL2
60ball FBGA
SSTL2
60ball FBGA
SSTL2
60ball FBGA
Interface
Package
Operating Frequencies
CC(DDR400@CL=3)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
*CL : CAS Latency
-
166MHz
200MHz
3-3-3
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
A2(DDR266@CL=2.0)
133MHz
133MHz
-
2-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
-
2.5-3-3
Rev. 0.0 October. 2004
DDR SDRAM 512Mb C-die (x4, x8, x16)
Ball Description (Bottom
View)
Preliminary
DDR SDRAM
128M x 4
1
2
3
7
8
9
VSSQ
NC
VSS
A
VDD
NC
VDDQ
NC
VDDQ
DQ3
B
DQ0
VSSQ
NC
NC
VSSQ
NC
C
NC
VDDQ
NC
NC
VDDQ
DQ2
D
DQ1
VSSQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
VREF
VSS
DM
F
NC
VDD
NC
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
64M x 8
1
2
3
7
8
9
VSSQ
DQ7
VSS
A
VDD
DQ0
VDDQ
NC
VDDQ
DQ6
B
DQ1
VSSQ
NC
NC
VSSQ
DQ5
C
DQ2
VDDQ
NC
NC
VDDQ
DQ4
D
DQ3
VSSQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
VREF
VSS
DM
F
NC
VDD
NC
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
32M x 16
1
2
3
7
8
9
VSSQ
DQ15
VSS
A
VDD
DQ0
VDDQ
DQ14
VDDQ
DQ13
B
DQ2
VSSQ
DQ1
DQ12
VSSQ
DQ11
C
DQ4
VDDQ
DQ3
DQ10
VDDQ
DQ9
D
DQ6
VSSQ
DQ5
DQ8
VSSQ
UDQS
E
LDQS
VDDQ
DQ7
VREF
VSS
UDM
F
LDM
VDD
NC
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
Organization
128Mx4
64Mx8
32Mx16
Row Address
A0~A12
A0~A12
A0~A12
Column Address
A0-A9, A11, A12
A0-A9, A11
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 0.0 October. 2004
DDR SDRAM 512Mb C-die (x4, x8, x16)
Package Physical Dimension
10.00 ± 0.10
Preliminary
DDR SDRAM
( Unit : mm )
1.00MAX
12.00 ± 0.10
12.00 ± 0.10
A
#A1 MARK(option)
B
3
2
1
0.80
1.00
0.50
5.50
1.00 x11 11.00
(Datum A)
0.50
12.00 ± 0.10
#A1
Top view
10.00 ± 0.10
0.80 x8 =
6.40
0.80 x4 = 3.20
WINDOW MOLD AREA
0.80 x2= 1.60
9
8
7
6
5
0.80 x2 = 1.60
4
A
B
(Datum B) C
D
E
F
G
H
J
K
L
M
60-∅0.45 ± 0.05
0.20 M A B
4-CORNER MARK(option)
(0.90)
(1.80)
(0.90)
Bottom view
60Ball FBGA 512Mb Package Dimension
Rev. 0.0 October. 2004
0.45 ± 0.05
1.20 MAX