DS21FT40
Four x Three 12 Channel E1 Framer
www.dalsemi.com
MULTI-CHIP MODULE FEATURES
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Twelve (12) completely independent
E1 Framers in one small 27 mm x 27 mm
Package
Each Multi-Chip Module (MCM) Contains
Three DS21Q44 Quad E1 Framer Die
Each Quad Framer can be concatenated into
a Single 8.192 MHz Backplane Data Stream
300–pin MCM 1.27 mm pitch BGA package
(27 mm X 27 mm)
Low Power 3.3V CMOS with 5V Tolerant
Input & Outputs
FUNCTIONAL DIAGRAM
Receive
Framer
Transmit
Formatter
FRAMER #1
FRAMER #2
FRAMER #3
ρρρ
Elastic
Store
Elastic
Store
FRAMER #12
Control Port
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FRAMER FEATURES
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All framers are fully independent; transmit
and receive sections of each framer are fully
independent
Frames to FAS, CAS, CCS, and CRC4
formats
Each framer contains dual two–frame elastic
store slip buffers that can connect to
asynchronous backplanes up to 8.192 MHz
8–bit parallel control port that can be used
directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)
Easy access to Si and Sa bits
Extracts and inserts CAS signaling
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Large counters for bipolar and code
violations, CRC4 code word errors, FAS
word errors, and E-bits
Programmable output clocks for Fractional
E1, per channel loopback, H0 and H12
applications
Integral HDLC controller with 64-byte
buffers. Configurable for Sa bits or DS0
operation
Detects and generates AIS, remote alarm,
and remote multiframe alarms
IEEE 1149.1 support
DESCRIPTION
The DS21FT40 MCM offers a high density packaging arrangement for the DS21Q44 E1 Enhanced Quad
Framer. Three DS21Q44 silicon die are packaged in a Multi-Chip Module (MCM) with the electrical
connections as shown in Figure 1-1. The DS21FT40 is closely related to the DS21FT44. Most of the
functions of the DS21FT44 are available on the DS21FT40. The differences are listed in Table 1-1.
Table 2-1 lists all of the signals on the MCM.
The DS21Q44 E1 Framer is an enhanced version of the DS21Q43 Quad E1 Framer. Each DS21Q44 die
contains four framers that are configured and read through a common microprocessor-compatible parallel
port. Each framer consists of a receive framer, receive elastic store, transmit formatter and transmit
elastic store. All four framers in the DS21Q44 are totally independent, they do not share a common
framing synchronizer. Also, the transmit and receive sides of each framer are totally independent. The
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DS21FT40
dual two-frame elastic stores contained in each of the four framers can be independently enabled and
disabled as required. The device fully meets all of the latest E1 specifications including CCITT/ITU
G.704, G.706, G.962, and I.431 as well as ETS 300 011 and ETS 300 233.
Functional Description
The receive side in each framer locates FAS frame and CRC and CAS multiframe boundaries as well as
detects incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If
needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered E1 data stream and an asynchronous backplane clock which is
provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048 MHz
clock or a 1.544 MHz clock. The RSYSCLK can be a burst clock with speeds up to 8.192 MHz.
The transmit side in each framer is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
E1 transmission.
Reader’s Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In
each 125 us frame, there are 32 8–bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and
received first. These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32.
Timeslot 0 is identical to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or
channel) is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted
first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following
abbreviations will be used:
FAS
CAS
MF
Si
CRC4
CCS
Sa
E-bit
Frame Alignment Signal
Channel Associated Signaling
Multiframe
International bits
Cyclical Redundancy Check
Common Channel Signaling
Additional bits
CRC4 Error Bits
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