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ALVD-0.750MHZ-H-P1-T

Description
PECL Output Clock Oscillator, 0.75MHz Nom, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size2MB,3 Pages
ManufacturerAbracon
Websitehttp://www.abracon.com/index.htm
Environmental Compliance  
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ALVD-0.750MHZ-H-P1-T Overview

PECL Output Clock Oscillator, 0.75MHz Nom, ROHS COMPLIANT, CERAMIC, SMD, 6 PIN

ALVD-0.750MHZ-H-P1-T Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerAbracon
Reach Compliance Codecompliant
Other featuresTRI-STATE; ENABLE/DISABLE FUNCTION; TAPE AND REEL
Maximum control voltage3 V
Minimum control voltage0.3 V
maximum descent time1.5 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate50 ppm
frequency stability35%
Manufacturer's serial numberALVD
Installation featuresSURFACE MOUNT
Nominal operating frequency0.75 MHz
Maximum operating temperature70 °C
Minimum operating temperature
Oscillator typePECL
physical size7.0mm x 5.0mm x 1.8mm
longest rise time1.5 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
WITH VOLTAGE CONTROL
ALVD
FEATURES:
• Based on a proprietary digital multiplier
• Tri-State Output
• Low Phase Jitter
• 3.3V +/- 5% operation
• Ceramic SMD, low profile package
APPLICATIONS:
• SONET, xDSL
• SDH, CPE
• STB
Pb
RoHS
Compliant
7.0 x 5.0 x 1.8mm
| | | | | | | | | | | | | | |
STANDARD SPECIFICATIONS:
P ARAMETERS
ABRACON P/N:
Frequency range:
Operating temperature:
Storage temperature:
Overall frequency stability:
Supply voltage (V
dd
):
Voltage control (V
C
):
Symmetry at 1/2 Vdd:
Output Level:
Pullability:
Tristate Function:
Aging per year:
RMS Phase Jitter:
Period Jitter (peak to peak):
Phase Noise:
ALVD Series
750 KHz to 800 MHz
0°C to +70°C (see options)
-55°C to +125°C
±50 ppm max. (see options)
3.3V ± 10%
0.3VDC min, 1.65VDC typ, 3.0 VDC max.
40/60% max.
See options (PECL, CMOS, or LVDS)
± 50ppm (see option)
"1" (V
IH
>= 0.7* Vdd) or open: Oscillation
"0" (V
IL
< 0.3* Vdd) : Hi Z
±5 ppm max.
3ps typical, 5ps max. (12KHz~20MHz)
35 ps typical
-112 dBc/Hz @ 1kHz Offset from 155.52MHz
-125 dBc/Hz @ 10kHz Offset from 155.52MHz
-123 dBc/Hz @ 100KHz Offset from 155.52MHz
-109 dBc/Hz @ 1kHz Offset from 622.08MHz
-110 dBc/Hz @ 10kHz Offset from 622.08MHz
-109 dBc/Hz @ 100KHz Offset from 622.08MHz
PECL:
Supply current (I
DD
):
25mA max (for Fo<24MHz),65mA max (for 24MHz<Fo<96MHz),100mA max (96MHz<Fo<700MHz)
Output Logic High:
V
dd
-1.025V min, V
dd
-0.880V max.
Output Logic Low:
V
dd
-1.810V min. V
dd
-1.620V max.
Symmetry (Duty Cycle):
45% min, 50% typ, 55% max,
Rise time:
0.6nSec typ,1.5nS max
Fall time:
0.6nSec typ, 1.5nS max
CMOS:
Supply current (I
DD
):
15
mA max (for Fo<24MHz),30mA max (for 24MHz<Fo<96MHz), 40mA max (96MHz<Fo<700MHz)
Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load]:
1.2ns typ, 1.6ns max.
Output Clock Duty Cycle [Measured @ 50% VDD]:
45% min, 50% typical, 55% max
LVDS:
Supply current (I
DD
):
25
mA max (for Fo<24MHz),45mA max (for 24MHz<Fo<96MHz),80mA max (96MHz<Fo<700MHz)
Output Clock Duty Cycle @ 1.25V:
45% min, 50% typical, 55% max
Output Differential Voltage (V
OD
):
247mV min, 355mV typical, 454mV max
VDD Magnitude Change (? V
OD
):
-50mV min, 50mV max
Output High Voltage :
V
OH
= 1.4V typical, 1.6V max.
Output Low Voltage:
V
OL
= 0.9V min, 1.1V typical
Offset Voltage [R
L
= 100?? : V
OS
= 1.125V min, 1.2V typical, 1.375V max
Offset Magnitude Change [R
L
= 100?? :
?
V
OS
= 0mV min, 3mV typical, 25mV max
Power-off Leakage (I
OXD
) [Vout=VDD or GND, VDD=0V] =
±1? A typical, ±10? A max.
Differential Clock Rise Time (t
r
) [R
L
=100? , CL=10pF]:
0.2nS min, 0.7nS typical, 1.0nS,max
Differential Clock Fall Time (t
f
) [R
L
=100? , CL=10pF]:
0.2nS min, 0.7nS typical, 1.0nS max
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
Revised: 07.22.09
30332
Esperanza, Rancho Santa Margarita, California
92688
tel 949-546-8000
|
fax 949-546-8001
| www.abracon.com
Visit www.abracon.com for Terms & Conditions of Sale
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