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CY7C63722C
CY7C63723C
CY7C63743C
enCoRe™ USB Combination Low-Speed
USB and PS/2 Peripheral Controller
Features
■
■
enCoRe™ USB - enhanced Component Reduction
❐
Internal oscillator eliminates the need for an external crystal
or resonator
❐
Interface can auto-configure to operate as PS/2 or USB with-
out the need for external components to switch between
modes (no General Purpose I/O [GPIO] pins needed to man-
age dual mode capability)
❐
Internal 3.3V regulator for USB pull-up resistor
❐
Configurable GPIO for real-world interface without external
components
Flexible, cost-effective solution for applications that combine
PS/2 and low-speed USB, such as mice, gamepads, joysticks,
and many others.
USB Specification Compliance
❐
Conforms to USB Specification, Version 2.0
❐
Conforms to USB HID Specification, Version 1.1
❐
Supports one low-speed USB device address and three data
endpoints
❐
Integrated USB transceiver
❐
3.3V regulated output for USB pull-up resistor
8-bit RISC microcontroller
❐
Harvard architecture
❐
6-MHz external ceramic resonator or internal clock mode
❐
12-MHz internal CPU clock
❐
Internal memory
❐
256 bytes of RAM
❐
8 Kbytes of EPROM
❐
Interface can auto-configure to operate as PS/2 or USB
❐
No external components for switching between PS/2 and
USB modes
❐
No GPIO pins needed to manage dual mode capability
I/O ports
❐
Up to 16 versatile GPIO pins, individually configurable
❐
High current drive on any GPIO pin: 50 mA/pin current sink
❐
Each GPIO pin supports high-impedance inputs, internal
pull-ups, open drain outputs or traditional CMOS outputs
❐
Maskable interrupts on all I/O pins
SPI serial communication block
❐
Master or slave operation
❐
2 Mbit/s transfers
Four 8-bit Input Capture registers
❐
Two registers each for two input pins
❐
Capture timer setting with five prescaler settings
❐
Separate registers for rising and falling edge capture
❐
Simplifies interface to RF inputs for wireless applications
Internal low-power wake-up timer during suspend mode
❐
Periodic wake-up with no external components
Optional 6-MHz internal oscillator mode
❐
Allows fast start-up from suspend mode
Watchdog Reset (WDR)
Low-voltage Reset at 3.75V
Internal brown-out reset for suspend mode
Improved output drivers to reduce EMI
Operating voltage from 4.0V to 5.5VDC
Operating temperature from 0°C to 70°C
CY7C63723C available in 18-pin SOIC, 18-pin PDIP
CY7C63743C available in 24-pin SOIC, 24-pin PDIP, 24-pin
QSOP
CY7C63722C available in DIE form
Industry standard programmer support
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Cypress Semiconductor Corporation
Document #: 38-08022 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 15, 2011
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CY7C63722C
CY7C63723C
CY7C63743C
Logic Block Diagram
XTALIN/P2.1
XTALOUT
Internal
Oscillator
Xtal
Oscillator
8-bit
RISC
Core
Wake-Up
Timer
RAM
256 Byte
12-bit
Timer
Capture
Timers
SPI
EPROM
8K Byte
Brown-out
Reset
Watch
Dog
Timer
Low
Voltage
Reset
Interrupt
Controller
USB
Engine
USB &
PS/2
Xcvr
Port 1
GPIO
Port 0
GPIO
3.3V
Regulator
VREG/P2.0
D+,D–
P1.0–P1.7
P0.0–P0.7
Functional Overview
enCoRe USB—The New USB Standard
Cypress has reinvented its leadership position in the low-speed
USB
market
with
a
new
family
of
innovative
microcontrollers. Introducing...enCoRe USB—“enhanced
Component Reduction.” Cypress has leveraged its design
expertise in USB solutions to create a new family of low-speed
USB microcontrollers that enables peripheral developers to
design new products with a minimum number of components. At
the heart of the enCoRe USB technology is the breakthrough
design of a crystalless oscillator. By integrating the oscillator into
our chip, an external crystal or resonator is no longer needed.
We have also integrated other external components commonly
found in low-speed USB applications such as pull-up resistors,
wake-up circuitry, and a 3.3V regulator. All of this adds up to a
lower system cost.
The CY7C637xxC is an 8-bit RISC one-time-programmable
(OTP) microcontroller. The instruction set has been optimized
specifically for USB and PS/2 operations, although the microcon-
trollers can be used for a variety of other embedded applications.
The CY7C637xxC features up to 16 GPIO pins to support USB,
PS/2 and other applications. The I/O pins are grouped into two
ports (Port 0 to 1) where each pin can be individually configured
as inputs with internal pull-ups, open drain outputs, or traditional
CMOS outputs with programmable drive strength of up to 50 mA
output drive. Additionally, each I/O pin can be used to generate
a GPIO interrupt to the microcontroller. Note the GPIO interrupts
all share the same “GPIO” interrupt vector.
The CY7C637xxC microcontrollers feature an internal oscillator.
With the presence of USB traffic, the internal oscillator can be set
to precisely tune to USB timing requirements (6 MHz ±1.5%).
Document #: 38-08022 Rev. *E
Optionally, an external 6-MHz ceramic resonator can be used to
provide a higher precision reference for USB operation. This
clock generator reduces the clock-related noise emissions
(EMI). The clock generator provides the 6- and 12-MHz clocks
that remain internal to the microcontroller.
The CY7C637xxC has 8 Kbytes of EPROM and 256 bytes of
data RAM for stack space, user variables, and USB FIFOs.
These parts include low-voltage reset logic, a Watchdog timer, a
vectored interrupt controller, a 12-bit free-running timer, and
capture timers. The low-voltage reset (LVR) logic detects when
power is applied to the device, resets the logic to a known state,
and begins executing instructions at EPROM address 0x0000.
LVR will also reset the part when V
CC
drops below the operating
voltage range. The Watchdog timer can be used to ensure the
firmware never gets stalled for more than approximately 8 ms.
The microcontroller supports 10 maskable interrupts in the
vectored interrupt controller. Interrupt sources include the USB
Bus-Reset, the 128-s and 1.024-ms outputs from the
free-running timer, three USB endpoints, two capture timers, an
internal wake-up timer and the GPIO ports. The timers bits cause
periodic interrupts when enabled. The USB endpoints interrupt
after USB transactions complete on the bus. The capture timers
interrupt whenever a new timer value is saved due to a selected
GPIO edge event. The GPIO ports have a level of masking to
select which GPIO inputs can cause a GPIO interrupt. For
additional flexibility, the input transition polarity that causes an
interrupt is programmable for each GPIO pin. The interrupt
polarity can be either rising or falling edge.
The free-running 12-bit timer clocked at 1 MHz provides two
interrupt sources as noted above (128
s
and 1.024 ms). The
timer can be used to measure the duration of an event under
firmware control by reading the timer at the start and end of an
Page 2 of 53
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CY7C63722C
CY7C63723C
CY7C63743C
event, and subtracting the two values. The four capture timers
save a programmable 8 bit range of the free-running timer when
a GPIO edge occurs on the two capture pins (P0.0, P0.1).
The CY7C637xxC includes an integrated USB serial interface
engine (SIE) that supports the integrated peripherals. The
hardware supports one USB device address with three
endpoints. The SIE allows the USB host to communicate with the
function integrated into the microcontroller. A 3.3V regulated
output pin provides a pull-up source for the external USB resistor
on the D– pin.
The USB D+ and D– USB pins can alternately be used as PS/2
SCLK and SDATA signals, so that products can be designed to
respond to either USB or PS/2 modes of operation. PS/2
operation is supported with internal pull-up resistors on SCLK
and SDATA, the ability to disable the regulator output pin, and an
interrupt to signal the start of PS/2 activity. No external compo-
nents are necessary for dual USB and PS/2 systems, and no
GPIO pins need to be dedicated to switching between modes.
Slow edge rates operate in both modes to reduce EMI.
Pin Configurations
Top View
CY7C63723C
18-pin SOIC/PDIP
P0.0
P0.1
P0.2
P0.3
P1.0
VSS
VPP
VREG/P2.0
XTALIN/P2.1
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P0.4
P0.5
P0.6
P0.7
P1.1
D+/SCLK
D–/SDATA
VCC
XTALOUT
CY7C63743C
24-pin SOIC/PDIP/QSOP
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
P1.4
P1.6
VSS
VPP
VREG/P2.0
XTALIN/P2.1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
P0.4
P0.5
P0.6
P0.7
P1.1
P1.3
P1.5
P1.7
D+/SCLK
D–/SDATA
VCC
XTALOUT
CY7C63722C-XC
DIE
3
2
1
25
24
23
P0.3
P1.0
P1.2
P1.4
P1.6
VSS
4
5
6
7
8
9
22
21
20
19
18
P0.2
P0.1
P0.0
P0.4
P0.5
P0.6
P0.7
P1.1
P1.3
P1.5
P1.7
VSS 10
VPP 11
VREG 12
XTALIN/P2.1
XTALOUT
VCC
D-/SDATA
13
14
15
16
17 D+/SCLK
Pin Definitions
Name
D–/SDATA,
D+/SCLK
P0[7:0]
I/O
I/O
I/O
CY7C63723C CY7C63743C CY7C63722C
18-Pin
12
13
1, 2, 3, 4,
15, 16, 17, 18
24-Pin
15
16
25-Pad
16
17
Description
USB differential data lines (D– and D+), or PS/2 clock
and data signals (SDATA and SCLK)
1, 2, 3, 4,
1, 2, 3, 4,
GPIO Port 0 capable of sinking up to 50 mA/pin, or
21, 22, 23, 24 22, 23, 24, 25 sinking controlled low or high programmable current.
Can also source 2 mA current, provide a resistive
pull-up, or serve as a high-impedance input. P0.0 and
P0.1 provide inputs to Capture Timers A and B, respec-
tively.
5, 6, 7, 8,
5, 6, 7, 8,
IO Port 1 capable of sinking up to 50 mA/pin, or sinking
17, 18, 19, 20 18, 19, 20, 21 controlled low or high programmable current. Can also
source 2 mA current, provide a resistive pull-up, or
serve as a high-impedance input.
12
13
10
14
11
9
13
14
11
15
12
9, 10
6-MHz ceramic resonator or external clock input, or
P2.1 input
6-MHz ceramic resonator return pin or internal oscillator
output
Programming voltage supply, ground for normal
operation
Voltage supply
Voltage supply for 1.3-k USB pull-up resistor (3.3V
nominal). Also serves as P2.0 input.
Ground
P1[7:0]
I/O
5, 14
XTALIN/P2.1
XTALOUT
V
PP
V
CC
VREG/P2.0
V
SS
IN
OUT
9
10
7
11
8
6
Document #: 38-08022 Rev. *E
Page 3 of 53
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CY7C63722C
CY7C63723C
CY7C63743C
Programming Model
Refer to the
CYASM Assembler User’s Guide
for more details on
firmware operation with the CY7C637xxC microcontrollers.
decremented again and the first byte is restored from memory
addressed by the PSP. After the program counter and flags have
been restored from stack, the interrupts are enabled. The effect
is to restore the program counter and flags from the program
stack, decrement the program stack pointer by two, and reenable
interrupts.
The call subroutine (CALL) instruction stores the program
counter and flags on the program stack and increments the PSP
by two.
The return from subroutine (RET) instruction restores the
program counter, but not the flags, from program stack and
decrements the PSP by two.
Note that there are restrictions in using the JMP, CALL, and
INDEX instructions across the 4-KByte boundary of the program
memory. Refer to the
CYASM Assembler User’s Guide
for a
detailed description.
Program Counter (PC)
The 14-bit program counter (PC) allows access for up to 8
Kbytes of EPROM using the CY7C637xxC architecture. The
program counter is cleared during reset, such that the first
instruction executed after a reset is at address 0x0000. This
instruction is typically a jump instruction to a reset handler that
initializes the application.
The lower 8 bits of the program counter are incremented as
instructions are loaded and executed. The upper six bits of the
program counter are incremented by executing an XPAGE
instruction. As a result, the last instruction executed within a
256-byte “page” of sequential code should be an XPAGE
instruction. The assembler directive “XPAGEON” will cause the
assembler to insert XPAGE instructions automatically. As
instructions can be either one or two bytes long, the assembler
may occasionally need to insert a NOP followed by an XPAGE
for correct execution.
The program counter of the next instruction to be executed, carry
flag, and zero flag are saved as two bytes on the program stack
during an interrupt acknowledge or a CALL instruction. The
program counter, carry flag, and zero flag are restored from the
program stack only during a RETI instruction.
Please note the program counter cannot be accessed directly by
the firmware. The program stack can be examined by reading
SRAM from location 0x00 and up.
8-bit Data Stack Pointer (DSP)
The data stack pointer (DSP) supports PUSH and POP instruc-
tions that use the data stack for temporary storage. A PUSH
instruction will pre-decrement the DSP, then write data to the
memory location addressed by the DSP. A POP instruction will
read data from the memory location addressed by the DSP, then
post-increment the DSP.
During a reset, the Data Stack Pointer will be set to zero. A PUSH
instruction when DSP equals zero will write data at the top of the
data RAM (address 0xFF). This would write data to the memory
area reserved for a FIFO for USB endpoint 0. In non-USB appli-
cations, this works fine and is not a problem.
For USB applications, the firmware should set the DSP to an
appropriate location to avoid a memory conflict with RAM
dedicated to USB FIFOs. The memory requirements for the USB
endpoints are shown in Section . For example, assembly instruc-
tions to set the DSP to 20h (giving 32 bytes for program and data
stack combined) are shown below.
MOV A,20h
; Move 20 hex into Accumulator (must be D8h
or less to avoid USB FIFOs)
SWAP A,DSP ; swap accumulator value into DSP register
8-bit Accumulator (A)
The accumulator is the general-purpose, do everything register
in the architecture where results are usually calculated.
8-bit Index Register (X)
The index register “X” is available to the firmware as an auxiliary
accumulator. The X register also allows the processor to perform
indexed operations by loading an index value into X.
8-bit Program Stack Pointer (PSP)
During a reset, the program stack pointer (PSP) is set to zero.
This means the program “stack” starts at RAM address 0x00 and
“grows” upward from there. Note that the program stack pointer
is directly addressable under firmware control, using the MOV
PSP,A instruction. The PSP supports interrupt service under
hardware control and CALL, RET, and RETI instructions under
firmware control.
During an interrupt acknowledge, interrupts are disabled and the
program counter, carry flag, and zero flag are written as two
bytes of data memory. The first byte is stored in the memory
addressed by the program stack pointer, then the PSP is incre-
mented. The second byte is stored in memory addressed by the
program stack pointer and the PSP is incremented again. The
net effect is to store the program counter and flags on the
program “stack” and increment the program stack pointer by two.
The return from interrupt (RETI) instruction decrements the
program stack pointer, then restores the second byte from
memory addressed by the PSP. The program stack pointer is
Address Modes
The CY7C637xxC microcontrollers support three addressing
modes for instructions that require data operands: data, direct,
and indexed.
Data
The “Data” address mode refers to a data operand that is actually
a constant encoded in the instruction. As an example, consider
the instruction that loads A with the constant 0x30:
■
MOV A, 30h
This instruction will require two bytes of code where the first byte
identifies the “MOV A” instruction with a data operand as the
second byte. The second byte of the instruction will be the
constant “0xE8h”. A constant may be referred to by name if a
prior “EQU” statement assigns the constant value to the name.
For example, the following code is equivalent to the example
shown above.
■
DSPINIT: EQU 30h
Document #: 38-08022 Rev. *E
Page 4 of 53
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