square pixels (based on the high-fill factor active pixel
sensor technology of FillFactory (US patent No. 6,225,670 and
others)).
Optical format: ½ optical inch
Pixel rate of 80 MHz
On-chip 10 bit ADCs
Full snapshot shutter.
Random programmable windowing.
48-pin LCC package
Sub sampling (Y direction)
Programmable read out direction (X and Y)
■
■
■
■
■
■
■
■
Applications
■
■
Machine Vision
Motion Tracking
Parameter
Typical View
½ inch
640 (H) x 480 (V)
9.9
μm
x 9.9
μm
Electronic Snapshot Shutter
80 MPS/80 MHz
250 fps (640 x 480)
10-bit, on-chip
3200 V.m2/W.s
17 V/lux.s
61 dB
Analog: 2.5V to 3.3V
Digital: 2.5V
I/O: 2.5V
190 mWatt
–40°C to 70°C
Mono
RGB Bayer Pattern
48-pins LCC
Overview
This document describes the interfacing and driving of the
LUPA-300 image sensor. This VGA-resolution CMOS active
pixel sensor features synchronous shutter and a maximal frame
rate of 250 fps in full resolution. The readout speed can be
boosted by means of sub sampling and windowed Region Of
Interest (ROI) readout. High dynamic range scenes can be
captured using the double and multiple slope functionality. User
programmable row and column start/stop positions allow
windowing. Sub sampling reduces resolution while maintaining
the constant field of view and an increased frame rate. The
programmable gain and offset amplifier maps the signal swing to
the ADC input range. A 10-bit ADC converts the analog data to
a 10-bit digital word stream. The sensor uses a 3-wire
Serial-Parallel (SPI) interface. It operates with a 3.3V and 2.5V
power supply and requires only one master clock for operation
up to 80 MHz pixel rate. It is housed in an 48-pin ceramic LCC
package.
The sensor is available in a monochrome version or Bayer (RGB)
patterned color filter array.
This data sheet allows the user to develop a camera-system
based on the described timing and interfacing.
Optical Format
Active Pixels
Pixel Size
Shutter Type
Maximum Data Rate/Master
Clock
Frame Rate
ADC Resolution
Responsivity
Dynamic Range
Supply Voltage
Power Consumption
Operating Temperature
Color Filter Array
Packaging
Cypress Semiconductor Corporation
Document Number: 001-00371 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 15, 2009
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CYIL1SM0300AA
Ordering Information
Marketing Part Number
CYIL1SM0300AA-QDC
CYIL1SM0300AA-QWC
CYIL1SE0300AA-QDC
CYIL1SM0300AA-WWC
CYIL1SM0300-EVAL
CYIL1SE0300-EVAL
Description
[1]
Mono with Glass
Mono without Glass
Color micro lens with Glass
Mono Wafer Sales
Mono Demo Kit
Color micro lens Demo Kit
Wafer Sales
Demo Kit
48-pin LCC
Package
Specifications
General Specifications
Parameter
Pixel Architecture
Pixel Size
Resolution
Pixel Rate
Shutter Type
Frame Rate
Specifications
6 transistor pixel
9.9 µm x 9.9 µm
640 x 480
80 MHz
Pipelined snapshot shutter
250 fps
Integration is possible during read out
Frame rate can be boosted by sub sampling and windowing
The pixel size and resolution result in a 6.3 mm x 4.7 mm optical
active area (1/2 inch)
Remarks
Electro-Optical Specifications
Parameter
FPN
PRNU
Conversion gain
Saturation charge
Sensitivity
Typical Specifications
2.5% RMS
2.5% RMS
34 uV/
e
-
35.000
e
-
3200 V.m2/W.s
17V/lux.s
Peak QE * FF
Dark current (at 21 °C)
Noise electrons
S/N ratio
Parasitic sensitivity
MTF
Power dissipation
45%
300mV/s
32
e
-
60.7 dB
1/5000
60%
160 mW
190 mW
Min: NA, Max: NA
Min: NA, Max: NA
Min: NA, Max: NA
Min: NA, Max: NA
Min: NA, Max: NA
Typical, not including output load
Typical, including output loads of 15 pF
Remarks
10% peak-to-peak, Min: NA, Max: 3.1%
Min: NA, Max: 3.1%
At output, Min: NA, Max: NA
Min: NA, Max: NA
Min: NA, Max: NA
Visible band only (180 lux = 1 W/m2)
Note
1. The LUPA-300 is also available in color or monochrome without the cover glass. Contact your local Cypress Sales office for more information.
Document Number: 001-00371 Rev. *F
Page 2 of 31
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CYIL1SM0300AA
Spectral Response Curve
Figure 2. Special Response of LUPA-300
0.16
0.14
0.12
Response (A/W)
0.1
0.08
0.06
0.04
0.02
0
400
500
600
700
Wavelength (nm)
800
900
1000
Photo-voltaic Response Curve
Figure 3. Photo-voltaic Response LUPA-300
1.2
1
Output Voltage (analog)
0.8
0.6
0.4
0.2
0
0.00E+00
1.00E+04
2.00E+04
3.00E+04
electrons
4.00E+04
5.00E+04
6.00E+04
7.00E+04
Document Number: 001-00371 Rev. *F
Page 3 of 31
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CYIL1SM0300AA
Features and General Specifications
Table 1. General Specifications
Feature
Electronic shutter type
Windowing (ROI)
Sub-sampling
Read out direction
Extended dynamic range
Programmable gain
Programmable offset
Digital output
Supply voltage VDD
Logic levels
Operational temperature range
Interface
Package
Power dissipation
Mass
Specification/Description
Full snapshot shutter (integration during read out is possible)
Randomly programmable ROI read out. Implemented as scanning of lines/columns from an
uploaded position
Sub sampling is possible (only in the Y-direction)
Sub-sampling pattern: Y0Y0Y0Y0
Read out direction can be reversed in X and Y
Multiple slope (up to 90 dB optical dynamic range)
Range x1 to x16, in 16 steps using 4-bits programming
256 steps (8 bit)
On-chip 10-bit ADCs at 80 Msamples/s
Nominal 2.5V (some supplies require 3.3V)
2.5V
–40°C to 70°C; with degradation of dark current
Serial-to Parallel Interface (SPI)
48-pin LCC
<190 mW
±1g
Electrical Specifications
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
IN
V
OUT
I
IO
T
L
DC input voltage
DC output voltage
DC current on any single pin
Lead temperature (5 seconds soldering)
Parameter
DC supply voltages
Value
–0.5 to 3.5
–0.5 to 3.5
–0.5 to 3.5
+/– 50
350
Unit
V
V
V
mA
ºC
Absolute Ratings are those values beyond which damage to the device may occur.
V
DD
= V
DDD
= V
DDA
(V
DDD
is supply to digital circuit, V
DDA
to analog circuit)
Document Number: 001-00371 Rev. *F
Page 4 of 31
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CYIL1SM0300AA
:
Table 3. Recommended Operating Conditions
Symbol
V
DDA
V
DDD
V
PIX
V
RES
V
MEM_H
V
ADC
T
A
A
L
Parameter
[2,3,4]
Power supply of the analog readout circuitry.
Digital power supply
Power supply of the analog pixel array
Power supply reset drivers
Power supply of the pixels memory element (high level)
Power supply of the on-chip ADCs
Commercial operating temperature.
Maximum lens angle
–40
2.5
2.5
Min
Typ
2.5
2.5
2.5
3.3
3.3
2.5
30
70
25
3.5
3.5
Max
Unit
V
V
V
V
V
V
°C
°
Sensor Architecture
The floor plan of the architecture is shown in
Figure 4.
The image
core consists of a pixel array, an X- and Y-addressing register,
pixel array drivers, and column amplifiers. The image sensor of
640 x 480 pixels is read out in progressive scan.
The architecture allows programmable addressing in the
x-direction in steps of 8 pixels and in the y-direction in steps of 1
pixel. The starting point of the address is uploadable by means
of the Serial Parallel Interface (SPI).
The PGAs amplify the signal from the column and add an offset
so the signal fits in the input range of the ADC. The four ADCs
then convert the signal to the digital domain. Pixels are selected
in a 4 * 1 kernel. Every ADC samples the signal from one of the
4 selected pixels. Sampling frequency is 20 MHz. The digital
outputs of the four ADCs are multiplexed to one output bus
operating at 80 MHz.
Figure 4. Floor Plan of the Sensor
On chip drivers
Y-shift register
Pixel array
640 x 480
Column amplifiers
X-shift register
PGA + ADC
PGA + ADC
Mux
PGA + ADC
PGA + ADC
Sequencer
10 bit output
Notes
2. All parameters are characterized for DC conditions after thermal equilibrium has been established.
3. Unused inputs must always be tied to an appropriate logic level, for example, either VDD or GND.
4. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is recommended that normal precautions
be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit.
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